MC9328MX1CVM15 Freescale, MC9328MX1CVM15 Datasheet - Page 6

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MC9328MX1CVM15

Manufacturer Part Number
MC9328MX1CVM15
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9328MX1CVM15

Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

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Signals and Connections
6
DMA_REQ
BIG_ENDIAN
ETMTRACESYNC
ETMTRACECLK
ETMPIPESTAT [2:0]
ETMTRACEPKT [7:0] ETM packet signals which are multiplexed with ECB, LBA, BCLK (burst clock), PA17, A [19:16].
CSI_D [7:0]
CSI_MCLK
CSI_VSYNC
CSI_HSYNC
CSI_PIXCLK
LD [15:0]
FLM/VSYNC
LP/HSYNC
LSCLK
ACD/OE
CONTRAST
SPL_SPR
PS
CLS
REV
SIM_CLK
SIM_RST
SIM_RX
Signal Name
DMA Request—external DMA request signal. Multiplexed with SPI1_SPI_RDY.
Big Endian—Input signal that determines the configuration of the external chip-select space. If it is
driven logic-high at reset, the external chip-select space will be configured to big endian. If it is driven
logic-low at reset, the external chip-select space will be configured to little endian. This input must not
change state after power-on reset negates or during chip operation.
ETM sync signal which is multiplexed with A24. ETMTRACESYNC is selected in ETM mode.
ETM clock signal which is multiplexed with A23. ETMTRACECLK is selected in ETM mode.
ETM status signals which are multiplexed with A [22:20]. ETMPIPESTAT [2:0] are selected in ETM
mode.
ETMTRACEPKT [7:0] are selected in ETM mode.
Sensor port data
Sensor port master clock
Sensor port vertical sync
Sensor port horizontal sync
Sensor port data latch clock
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off.
Frame Sync or Vsync—This signal also serves as the clock signal output for the gate
driver (dedicated signal SPS for Sharp panel HR-TFT).
Line pulse or H sync
Shift clock
Alternate crystal direction/output enable.
This signal is used to control the LCD bias voltage as contrast control.
Program horizontal scan direction (Sharp panel dedicated signal).
Control signal output for source driver (Sharp panel dedicated signal).
Start signal output for gate driver. This signal is an inverted version of PS (Sharp panel dedicated
signal).
Signal for common electrode driving signal preparation (Sharp panel dedicated signal).
SIM Clock
SIM Reset
Receive Data
Table 2. i.MX1 Signal Descriptions (Continued)
MC9328MX1 Technical Data, Rev. 7
CMOS Sensor Interface
LCD Controller
DMA
ETM
SIM
Function/Notes
Freescale Semiconductor

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