MCIMX356AVM5B Freescale, MCIMX356AVM5B Datasheet - Page 7

• Manufacturer Part Number: MCIMX356AVM5B
• Manufacturer: Freescale

Specifications of MCIMX356AVM5B

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Table 3
2.5
Table 4
modules, see the MCIMX35 reference manual.
Freescale Semiconductor
ARM11 or
ARM1136
Mnemonic
Acronym
1-WIRE
Block
ASRC
Core
•
•
•
•
•
•
•
•
•
•
Branch prediction with return stack
Low-interrupt latency
Instruction and data memory management units (MMUs), managed using micro TLB structures
backed by a unified main TLB
Instruction and data L1 caches, including a non-blocking data cache with hit-under-miss
Virtually indexed/physically addressed L1 caches
64-bit interface to both L1 caches
Write buffer (bypassable)
High-speed Advanced Micro Bus Architecture (AMBA)
Vector floating point co-processor (VFP) for 3D graphics and hardware acceleration of other
floating-point applications
ETM
summarizes information about the i.MX35 core.
shows an alphabetical listing of the modules in the MCIMX35. For extended descriptions of the
Module Inventory
1-Wire
interface
Asynchronous
sample rate
converter
Block Name
ARM1136
Platform
™
Name
Core
and JTAG-based debug support
The ARM1136™ platform consists of the ARM1136JF-S core, the ETM
real-time debug modules, a 6 × 5 multi-layer AHB crossbar switch (MAX), and
a vector floating processor (VFP).
The i.MX35 provides a high-performance ARM11 microprocessor core and
highly integrated system functions. The ARM Application Processor (AP) and
other subsystems address the needs of the personal, wireless, and portable
product market with integrated peripherals, advanced processor core, and
power management capabilities.
i.MX35 Applications Processors for Automotive Products, Rev. 9
ARM
SDMA
Domain
1
Table 4. Digital and Analog Modules
ARM1136
platform
peripherals
Connectivity
peripherals
Subsystem
Table 3. i.MX35 Core
Brief Description
1-Wire provides the communication line to a 1-Kbit add-only
memory. the interface can send or receive 1 bit at a time.
The ASRC is designed to convert the sampling rate of a signal
associated to an input clock into a signal associated to a different
output clock. It supports a concurrent sample rate conversion of
about –120 dB THD+N. The sample rate conversion of each
channel is associated to a pair of incoming and outgoing sampling
rates.
™
L2 interface
Brief Description
Integrated Memory
• 16-Kbyte
• 16-Kbyte data
• 128-Kbyte L2
• 32-Kbyte ROM
• 128-Kbyte RAM
instruction cache
cache
cache
Features
7