MCIMX356AVM5B Freescale, MCIMX356AVM5B Datasheet - Page 68
MCIMX356AVM5B
Manufacturer Part Number
MCIMX356AVM5B
Description
Manufacturer
Freescale
Datasheet
1.MCIMX356AVM5B.pdf
(148 pages)
Specifications of MCIMX356AVM5B
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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inserted in between EAV and SAV code. The CSI decodes and filters out the timing coding from the data
stream, thus recovering SENSB_VSYNC and SENSB_HSYNC signals for internal use.
4.9.12.2.2
The SENSB_VSYNC, SENSB_HSYNC, and SENSB_PIX_CLK signals are used in this mode. See
Figure
A frame starts with a rising edge on SENSB_VSYNC (all the timing corresponds to straight polarity of the
corresponding signals). Then SENSB_HSYNC goes to high and hold for the entire line. The pixel clock
is valid as long as SENSB_HSYNC is high. Data is latched at the rising edge of the valid pixel clocks.
SENSB_HSYNC goes to low at the end of the line. Pixel clocks then become invalid and the CSI stops
receiving data from the stream. For the next line, the SENSB_HSYNC timing repeats. For the next frame,
the SENSB_VSYNC timing repeats.
4.9.12.2.3
The timing is the same as the gated-clock mode (described in
except for the SENSB_HSYNC signal, which is not used. See
valid and will cause data to be latched into the input FIFO. The SENSB_PIX_CLK signal is inactive (states
low) until valid data is going to be transmitted over the bus.
68
45.
SENSB_DATA[9:0]
SENSB_PIX_CLK
SENSB_DATA[7:0]
SENSB_HSYNC
SENSB_VSYNC
SENSB_PIX_CLK
SENSB_VSYNC
Gated Clock Mode
Non-Gated Clock Mode
Start of Frame
Start of Frame
i.MX35 Applications Processors for Automotive Products, Rev. 9
invalid
invalid
Figure 46. Non-Gated Clock Mode Timing Diagram
nth frame
nth frame
Figure 45. Gated Clock Mode Timing Diagram
1st byte
1st byte
Active Line
n+1th frame
invalid
n+1th frame
Section 4.9.12.2.2, “Gated Clock
invalid
Figure
46. All incoming pixel clocks are
1st byte
1st byte
Freescale Semiconductor
Mode”),
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