MCIMX31DVMN5D Freescale, MCIMX31DVMN5D Datasheet - Page 94

• Manufacturer Part Number: MCIMX31DVMN5D
• Manufacturer: Freescale

Specifications of MCIMX31DVMN5D

• Operating Temperature (min): -20C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

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2
Electrical Characteristics
4.3.22
This section describes the electrical information of SSI. Note the following pertaining to timing
information:
4.3.22.1 SSI Transmitter Timing with Internal Clock
Figure 80
94
SJ11
SJ12
SJ13
On cases where SDMA TAP is put in the chain, the max TCK frequency is limited by max ratio of 1:8 of SDMA core frequency
to TCK limitation. This implies max frequency of 8.25 MHz (or 121.2 ns) for 66 MHz IPG clock.
V
ID
M -
•
•
•
•
mid point voltage
TCK low to TDO high impedance
TRST assert time
TRST set-up time to TCK low
All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0)
and a non-inverted frame sync (TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the clock signal STCK/SRCK and/or
the frame sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX signals when SSI is being used for data transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will be same as that of Tx
Data (for example, during AC97 mode of operation).
depicts the SSI transmitter timing with internal clock, and
SSI Electrical Specifications
Table 58. SJC Timing Parameters (continued)
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Parameter
Table 59
Min
100
40
—
All Frequencies
lists the timing parameters.
Freescale Semiconductor
Max
44
—
—
Unit
ns
ns
ns