MCIMX31LDVMN5D Freescale, MCIMX31LDVMN5D Datasheet - Page 46
MCIMX31LDVMN5D
Manufacturer Part Number
MCIMX31LDVMN5D
Description
Manufacturer
Freescale
Datasheet
1.MCIMX31LDVMN5D.pdf
(118 pages)
Specifications of MCIMX31LDVMN5D
Operating Temperature (min)
-20C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant
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Electrical Characteristics
46
1
Timing parameters are relevant only to SDR SDRAM. For the specific DDR SDRAM data related timing parameters, see
Table 37
SD10
SD9
ID
and
Active to read/write command period
Data out hold time
Table
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value. SD1 + SD2 does not exceed 7.5 ns for 133 MHz.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is,
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
Table 33. DDR/SDR SDRAM Read Cycle Timing Parameters (continued)
38.
1
Table 33
MCIMX31/MCIMX31L Technical Data, Rev. 4.3
Parameter
indicates SDRAM requirements. All output signals
NOTE
Symbol
tOH
tRC
Min
1.8
10
Freescale Semiconductor
Max
—
—
clock
Unit
ns
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