MC9328MX1VM20 Freescale, MC9328MX1VM20 Datasheet - Page 30

MC9328MX1VM20

Manufacturer Part Number
MC9328MX1VM20
Description
Manufacturer
Freescale
Datasheet

Specifications of MC9328MX1VM20

Operating Temperature (min)
0C
Operating Temperature (max)
70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC9328MX1VM20
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MC9328MX1VM20R2
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Functional Description and Application Information
4.4.1
The DTACK signal is the external input data acknowledge signal. When using the external DTACK signal
as a data acknowledge signal, the bus time-out monitor generates a bus error when a bus cycle is not
terminated by the external DTACK signal after 1022 HCLK counts have elapsed. Only the CS5 group
supports DTACK signal function when the external DTACK signal is used for data acknowledgement.
4.4.2
Figure 6
of measure for this figure are found in the associated tables.
30
1
Ref No.
Clock refers to the system clock signal, HCLK, generated from the System DPLL
10a
4a
4b
4c
4d
5a
5b
5c
5d
6a
6b
6c
7a
7b
7c
7d
8a
8b
9a
9b
9c
through
DTACK Signal Description
DTACK Signal Timing
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Clock
Read Data setup time
Read Data hold time
Clock
Clock
Clock
DTACK setup time
Figure 9
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
rise to Burst Clock fall
rise to Output Enable Valid
rise to Output Enable Invalid
fall to Output Enable Valid
fall to Output Enable Invalid
rise to Enable Bytes Valid
rise to Enable Bytes Invalid
fall to Enable Bytes Valid
fall to Enable Bytes Invalid
fall to Load Burst Address Valid
fall to Load Burst Address Invalid
rise to Load Burst Address Invalid
rise to Burst Clock rise
fall to Burst Clock rise
fall to Burst Clock fall
rise to Write Data Valid
fall to Write Data Invalid
rise to Write Data Invalid
Table 12. EIM Bus Timing Parameter Table (Continued)
show the access cycle timing used by chip-select 5. The signal values and units
Parameter
MC9328MX1 Technical Data, Rev. 7
2.32
2.11
2.38
2.17
1.91
1.81
1.97
1.76
2.07
1.97
1.91
1.61
1.61
1.55
1.55
5.54
1.81
1.45
1.63
2.52
Min
0
1.8 ± 0.1 V
Typical
2.62
2.52
2.69
2.59
2.52
2.42
2.59
2.48
2.79
2.79
2.62
2.62
2.62
2.48
2.59
2.72
2.48
Max
6.85
6.55
7.04
6.73
5.54
5.69
5.38
6.73
6.83
6.45
5.64
5.84
5.59
5.80
6.85
5.69
5.24
1.62
Min
2.3
2.1
2.3
2.1
1.9
1.8
1.9
1.7
2.0
1.9
1.9
1.6
1.6
1.5
1.5
5.5
1.8
1.4
2.5
0
3.0 ± 0.3 V
Typical
2.6
2.5
2.6
2.5
2.5
2.4
2.5
2.4
2.7
2.7
2.6
2.6
2.6
2.4
2.5
2.7
2.4
Freescale Semiconductor
Max
6.8
6.5
6.8
6.5
5.5
5.2
5.5
5.2
6.5
6.6
6.4
5.6
5.8
5.4
5.6
6.8
5.5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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