PPC405GPR-3KB266 Applied Micro Circuits Corporation, PPC405GPR-3KB266 Datasheet - Page 51

• Manufacturer Part Number: PPC405GPR-3KB266
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GPR-3KB266

• Family Name: 405GPr
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 266MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / RoHS Status: Compliant

Revision 2.05 – March 24, 2008
Strapping
When the SysReset input is driven low by an external device (system reset), the state of certain I/O pins is read to
enable default initial conditions prior to PPC405GPr start-up. The actual capture instant is the nearest SysClk edge
before the deassertion of reset. These pins must be strapped using external pull-up (logical 1) or pull-down
(logical 0) resistors to select the desired default conditions. The recommended pull-up is 3kΩ to +3.3V or 10kΩ to
+5V. The recommended pull-down is 1KΩ to GND. These pins are use for strap functions only during reset. They
are used for other signals during normal operation. The following tables list the strapping pins along with their
functions and strapping options. The signal names assigned to the pins for normal operation follow the pin
number.
The PPC405GPr can be used as a replacement for the PPC405GP. When the PPC405GPr is used for this
purpose, it should be strapped to operate in the PPC405GPr Legacy Mode. This option is selected by strapping
ball D20 (GPIO24) low (0). If Legacy Mode is selected, the “PPC405GPr Legacy Mode Strapping Pin Assignments”
table should be used to determine the strapping options. To operate the chip as a PPC405GPr, strap D20
(GPIO24) high (1) and use “PPC405GPr New Mode Strapping Pin Assignments” on page 53 to determine the
strapping options.
AMCC
PPC405GPr Legacy Mode Strapping Pin Assignments
PLL Tuning
for 6
for 7 < M
for 12 < M
PLL Forward Divider
PLL Feedback Divider
PLB Divider from CPU
≤
M
≤
≤
≤
Data Sheet
1
12 use choice 5
32 use choice 6
7 use choice 3
Function
2
2
2
Choice 1; TUNE[9:0] = 1010111100
Choice 2; TUNE[9:0] = 0100111000
Choice 3; TUNE[9:0] = 0100110110
Choice 4; TUNE[9:0] = 0100111100
Choice 5; TUNE[9:0] = 0100111000
Choice 6; TUNE[9:0] = 1000111100
Choice 7; TUNE[9:0] = 1000111110
Choice 8; TUNE[9:0] = 1011111110
405GPr – Power PC 405GPr Embedded Processor
Bypass mode
Divide by 3
Divide by 4
Divide by 6
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Divide by 1
Divide by 2
Divide by 3
Divide by 4
Option
(Sheet 1 of 2)
UART0_Tx
EMCTxD3
DMAAck0
DMAAck2
AF3
D16
B14
P25
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Ball Strapping
UART0_DTR
EMCTxD2
DMAAck1
DMAAck3
AF2
B15
C12
L24
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
UART0_RTS
AD16
0
1
0
1
0
1
0
1
51