PPC405GP-3KE200C Applied Micro Circuits Corporation, PPC405GP-3KE200C Datasheet - Page 44

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PPC405GP-3KE200C

Manufacturer Part Number
PPC405GP-3KE200C
Description
Manufacturer
Applied Micro Circuits Corporation
Datasheet

Specifications of PPC405GP-3KE200C

Family Name
405GP
Device Core
PowerPC
Device Core Size
32b
Frequency (max)
200MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
2.5V
Operating Supply Voltage (max)
2.7V
Operating Supply Voltage (min)
2.3V
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
456
Package Type
EBGA
Lead Free Status / RoHS Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PPC405GP-3KE200C
Manufacturer:
VIOCR
Quantity:
200
405GP – Power PC 405GP Embedded Processor
44
Peripheral Interface Clock Timings
PCIClk input frequency (asynchronous mode)
PCIClk period (asynchronous mode)
PCI Clock frequency (synchronous mode)
PCI Clock period (synchronous mode - Note 2)
PCIClk input high time
PCIClk input low time
EMCMDClk output frequency
EMCMDClk period
EMCMDClk output high time
EMCMDClk output low time
PHYTxClk input frequency
PHYTxClk period
PHYTxClk input high time
PHYTxClk input low time
PHYRxClk input frequency
PHYRxClk period
PHYRxClk input high time
PHYRxClk input low time
PerClk output frequency–133MHz
PerClk period–133MHz
PerClk output frequency–200MHz
PerClk period–200MHz
PerClk output frequency–266MHz
PerClk period–266MHz
PerClk output high time
PerClk output low time
PerClk clock edge stability (phase jitter, cycle to cycle)
UARTSerClk input frequency (Note 3)
UARTSerClk period
UARTSerClk input high time
UARTSerClk input low time
TmrClk input frequency–133MHz
TmrClk period–133MHz
TmrClk input frequency–200MHz
TmrClk period–200MHz
TmrClk input frequency–266MHz
TmrClk period–266MHz
TmrClk input high time
TmrClk input low time
Note:
1. In asynchronous PCI mode the minimum PCIClk frequency is 1/8 the PLB Clock. Refer to the PowerPC 405GP Embedded Processor
2. In synchronous PCI mode the PCI clock is derived from SysClk and the PCIClk input pin is unused.
3. T
User’s Manual for more information.
parts.
OPB
is the period in ns of the OPB clock. The maximum OPB clock frequency is 50 MHz for 200MHz parts and 66.66MHz for 266MHz
Parameter
40% of nominal period
40% of nominal period
35% of nominal period
35% of nominal period
35% of nominal period
35% of nominal period
45% of nominal period
45% of nominal period
40% of nominal period
40% of nominal period
2T
T
T
Note 1
OPB
OPB
Min
400
160
160
OPB
2.5
2.5
15
25
30
40
40
30
20
15
30
20
15
+1
+1
+2
Revision 2.05 – August 19, 2008
60% of nominal period
60% of nominal period
55% of nominal period
55% of nominal period
60% of nominal period
60% of nominal period
1000/(2T
Data Sheet
Note 1
66.66
33.33
33.33
66.66
33.33
66.66
± 0.3
Max
400
400
2.5
40
25
25
50
50
OPB
+2ns)
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AMCC

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