MC68331CEH16 Freescale, MC68331CEH16 Datasheet - Page 55

• Manufacturer Part Number: MC68331CEH16
• Manufacturer: Freescale

Specifications of MC68331CEH16

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Program Memory Type: ROMLess
• Lead Free Status / RoHS Status: Compliant

PORTQS — Port QS Data Register
PQSPAR — PORT QS Pin Assignment Register
DDRQS — PORT QS Data Direction Register
MC68331TS/D
RESET:
15
15
0
0
PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data present on the pins.
To avoid driving undefined data, first write a byte to PORTQS, then configure DDRQS.
Clearing a bit in the PQSPAR assigns the corresponding pin to general-purpose I/O; setting a bit as-
signs the pin to the QSPI. The PQSPAR does not affect operation of the SCI.
PQSPA6 PQSPA5 PQSPA4 PQSPA3
14
0
13
0
NOT USED
12
0
Freescale Semiconductor, Inc.
NOTES:
PQSPAR Field
11
For More Information On This Product,
0
1. PQS2 is a digital I/O pin unless the SPI is enabled
2. PQS7 is a digital I/O pin unless the SCI transmitter
(SPE in SPCR1 set), in which case it becomes SPI
serial clock SCK.
is enabled (TE in SCCR1 = 1), in which case it be-
comes SCI serial output TXD.
PQSPA0
PQSPA1
PQSPA2
PQSPA3
PQSPA4
PQSPA5
PQSPA6
PQSPA7
Table 23 QSPAR Pin Assignments
10
0
0
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PQSPA1 PQSPA0
9
0
PQSPAR Bit
8
8
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0
PQS7
7
0
7
0
RESET:
PQS6
6
0
6
0
Pin Function
PCS0/SS
PQS2
PQS7
PQS0
PQS1
PQS3
PQS4
PQS5
PQS6
MISO
MOSI
PCS1
PCS2
PCS3
SCK
TXD
PQS5
5
0
5
0
1
2
PQS4
4
0
4
0
PQS3
3
0
3
0
PQS2
2
0
2
0
PQS1
$YFFC14
1
0
$YFFC16
$YFFC17
1
0
PQS0
0
0
0
0
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