MC68331CEH16 Freescale, MC68331CEH16 Datasheet - Page 28

• Manufacturer Part Number: MC68331CEH16
• Manufacturer: Freescale

Specifications of MC68331CEH16

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Program Memory Type: ROMLess
• Lead Free Status / RoHS Status: Compliant

3.5 Chip Selects
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Byte to 8-Bit Port (Even/Odd)
Byte to 16-Bit Port (Even)
Byte to 16-Bit Port (Odd)
Word to 8-Bit Port (Aligned)
Word to 8-Bit Port (Misaligned)
Word to 16-Bit Port (Aligned)
Word to 16-Bit Port (Misaligned)
3 Byte to 8-Bit Port (Aligned)
3 Byte to 8-Bit Port (Misaligned)
3 Byte to 16-Bit Port (Aligned)
3 Byte to 16-Bit Port (Misaligned)
Long Word to 8-Bit Port (Aligned)
Long Word to 8-Bit Port (Misaligned)
Long Word to 16-Bit Port (Aligned)
Long Word to 16-Bit Port (Misaligned)
NOTES:
Typical microcontrollers require additional hardware to provide external chip-select signals. Twelve in-
dependently programmable chip selects provide fast two-cycle access to external memory or peripher-
als. Address block sizes of 2 Kbytes to 1 Mbyte can be selected.
Chip-select assertion can be synchronized with bus control signals to provide output enable, read/write
strobes, or interrupt acknowledge signals. Logic can also generate DSACK signals internally. A single
DSACK generator is shared by all circuits. Multiple chip selects assigned to the same address and con-
trol must have the same number of wait states.
Chip selects can also be synchronized with the ECLK signal available on ADDR23.
When a memory access occurs, chip-select logic compares address space type, address, type of ac-
cess, transfer size, and interrupt priority (in the case of interrupt acknowledge) to parameters stored in
chip-select registers. If all parameters match, the appropriate chip-select signal is asserted. Select sig-
nals are active low. Refer to the following block diagram of a single chip-select circuit.
1. Operands in parentheses are ignored by the CPU32 during read cycles.
2. Three-byte transfer cases occur only as a result of a long word to byte transfer.
3. The CPU32 does not support misaligned word or long-word transfers.
Transfer Case
2
Freescale Semiconductor, Inc.
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3
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For More Information On This Product,
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Table 11 Operand Alignment
Go to: www.freescale.com
SIZ1
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
SIZ0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
ADDR0
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
DSACK1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
DSACK0
X
X
X
X
X
X
X
X
0
0
0
0
0
0
0
DATA
[15:8]
(OP0)
(OP0)
(OP0)
(OP0)
MC68331TS/D
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
OP0
DATA
(OP0)
(OP0)
(OP1)
(OP0)
(OP1)
(OP0)
(OP1)
(OP0)
[7:0]
OP0
OP1
OP0
OP1
OP0
OP1
OP0