NS7520B-1-C55 Digi International, NS7520B-1-C55 Datasheet - Page 18
![no-image](/images/manufacturer_photos/0/1/193/digi_international_sml.jpg)
NS7520B-1-C55
Manufacturer Part Number
NS7520B-1-C55
Description
IC ARM MICROPROCESSOR 177BGA
Manufacturer
Digi International
Series
NET+ARM®r
Specifications of NS7520B-1-C55
Applications
Network Processor
Core Processor
ARM7
Program Memory Type
External Program Memory
Controller Series
-
Ram Size
External
Interface
EBI/EMI, Ethernet, DMA, SPI, UART
Number Of I /o
16
Voltage - Supply
1.4 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
177-LFBGA
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
NS7520B-1-C55
Manufacturer:
IR
Quantity:
4 954
Company:
Part Number:
NS7520B-1-C55
Manufacturer:
Digi International
Quantity:
10 000
Part Number:
NS7520B-1-C55
Manufacturer:
NETARM
Quantity:
20 000
Notes:
1
2
1 4
PORTC5
PORTC4
PORTC3
PORTC2
PORTC1
PORTC0
G e n e r a l P u r p o s e I / O
GPIO signal
RESET output indicates the reset state of the NS7520. PORTC4 persists beyond the negation of
RESET_ for approximately 512 clock cycles if the PLL is disabled. When the PLL is enabled,
PORTC4 persists beyond the negation of RESET_ to allow for PLL lock for 100 microseconds
times the ratio of the VCO to XTALA.
This GPIO is left in output mode active following a hardware RESET.
PORTC[3:0] pins provide level-sensitive interrupts. The inputs do not need to be synchronous
to any clock. The interrupt remains active until cleared by a change in the input signal level.
1
2
2
2
2
RTSB_
RXCB/RIB_/
OUT1B_
RXDB
DSRB_
CTSB_
TXCB/
OUT2B_/
DCDB_
Serial
signal
N S 7 5 2 0 D a t a s h e e t
REJECT_
RESET_
LIRQ3/
DACK2_
LIRQ2/RPSF_
LIRQ1/
DONE2_(O)
LIRQ0/
DONE2_(I)
Other
signal
F15 U
F12 U
F13 U
E15 U
E12 U
E14 U
Pin
I/O
I/O
I/O
I/O
I/O
I/O
I/O
0 3 / 2 0 0 6
2
2
2
2
2
2
OD
Channel 2 RTS_
Pgm’able Out/
Channel 2
RXCLK/Channel 2
ring signal/
Channel 2 SPI
clock (CLK)
Channel 2 RXD
Channel 2 DSR_
Channel 2 CTS_
Pgm’able Out/
Channel 2 DCD/
Channel 2 SPI
enable (SEL_)/
Channel 2 TXCLK
Serial channel
description
CAM reject
RESET output
Level sensitive IRQ /
DMA channel 4/6
ACK
Level sensitive IRQ/
CAM request
Level sensitive IRQ /
DMA channel 4/6
DONE_Out
Level sensitive IRQ /
DMA channel 4/6
DONE_In
Other
description