STPCC5HEBC STMicroelectronics, STPCC5HEBC Datasheet - Page 68

• Manufacturer Part Number: STPCC5HEBC
• Description: IC SYSTEM-ON-CHIP X86 388-PBGA
• Manufacturer: STMicroelectronics
• Series: -r

Specifications of STPCC5HEBC

• Applications: Set-Top Boxes, TV
• Core Processor: x86
• Program Memory Type: External Program Memory
• Controller Series: STPC® Consumer-II
• Ram Size: External
• Interface: EBI/EMI, I²C, IDE, ISA, Local Bus
• Number Of I /o: -
• Voltage - Supply: 2.45 V ~ 3.6 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: *
• Package / Case: *
• Lead Free Status / RoHS Status: Not Compliant

DESIGN GUIDELINES
For other implementations like 32-bit SDRAM
devices, refers to the SDRAM controller signal
6.3.4. PCI BUS
The PCI bus is always active and the following
control signals must be pulled-up to 3.3V or 5V
through 2K2 resistors even if this bus is not
connected to an external device: FRAME#,
TRDY#, IRDY#, STOP#, DEVSEL#, LOCK#,
SERR#, PCI_REQ#[2:0].
68/93
Address Mapping: 16 Mbit - 2 internal banks
STPC I/F
RAS Address A11
CAS Address A11
Address Mapping: 64/128 Mbit - 2 internal banks
STPC I/F
RAS Address A11
CAS Address A11
Address Mapping: 64/128 Mbit - 4 internal banks
STPC I/F
RAS Address A11
CAS Address A11
DIMM Pin Number
SDRAM Density
Internal Banks
123
126
122
...
39
BA0
BA0
BA0
MA12 MA11 MA10 MA9
A24
0
BA1
A12
A12
PCICLKO
PCICLKI
A23
0
MA11 MA10 MA9
A24
0
BA0 (MA11)
MA[10:0]
2 Banks
16 Mbit
Figure 6-7. Typical PCI clock routing
A22
A22
0
A23
MA10 MA9
0
0
-
-
-
0 - 22
Table 6-5. Address Mapping
Release 1.5 - January 29, 2002
Table 6-4. DIMM Pinout
A21
A24
A21
A26
A22
A26
0 - 33pF
10 - 33
MA8
A2
A23
MA8
A20
A25
MA8
A21
A25
BA0 (MA13)
64/128 Mbit
MA[10:0]
2 Banks
MA11
MA12
MA7
A19
A10
MA7
A19
A10
MA7
A20
A10
-
multiplexing and address mapping described in
the following
PCI_CLKO must be connected to PCI_CLKI
through a 10 to 33 Ohms resistor.
shows a typical implementation.
For more information on layout constraints, go to
the place and route recommendations section.
PCICLKA
PCICLKB
PCICLKC
MA6
A18
A9
MA6
A18
A9
MA6
A19
A9
A17
MA5
A17
A8
A18
MA5
A8
MA5
A8
Table 6-4
BA1 (MA12)
BA0 (MA13)
64/128 Mbit
MA[10:0]
4 Banks
MA11
MA4
A16
A7
MA4
A16
A7
MA4
A17
A7
-
and
MA3
A15
A6
MA3
A15
A6
MA3
A16
A6
Device A
Device B
Device C
Table
MA2
A14
A5
MA2
A14
A5
MA2
A15
A5
6-5.
CS2# (MA11)
CS3# (MA12)
CS3# (BA1)
STPC I/F
MA[10:0]
MA1
A13
A4
MA1
A13
A4
MA1
A14
A4
BA0
Figure 6-7
A12
A12
A13
MA0
A3
MA0
A3
MA0
A3