STA8088EXA STMicroelectronics, STA8088EXA Datasheet - Page 21

• Manufacturer Part Number: STA8088EXA
• Manufacturer: STMicroelectronics

Specifications of STA8088EXA

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Applications: Telematic
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.1V
• Operating Supply Voltage (typ): 1.2V
• Operating Supply Voltage (max): 1.3V
• Package Type: TFBGA
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

STA8088EX
3.4.4
SSP features
In both master and slave configurations, the SSP has the following features:
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UART
The UARTx (x = 0|1|2) performs serial-to-parallel conversion on data asynchronously
received from a peripheral device on URXDx pin, and parallel-to-serial conversion on data
written by CPU for transmission on UTXDx pin. The transmit and receive paths are buffered
with internal FIFO memories allowing up to 64 data byte for transmission, and 64 data byte
with 4-bit status (break, frame, parity, and overrun) for receive.
UART Features
The UARTx (x = 0|1|2) are Universal Asynchronous Receiver/Transmitter that support much
of the functionality of the industry-standard 16C650 UART. The main features are:
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These UARTs vary from industry-standard 16C650 on some minor points which are:
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Parallel-to-serial conversion on data written to an internal 32-bit wide, 32-location deep
transmit FIFO
Serial-to-parallel conversion on received data, buffering it in a 32-bit wide, 32-location
deep receive FIFO
Programmable data frame size from 4 to 32 bits,
Programmable clock bit rate and prescaler
Programmable clock phase and polarity in SPI mode
Programmable baud rates up to UARTCLK / 16 (3.0 Mbps with UARTCLK at 48 MHz),
or up to UARTCLK / 8 (6.0 Mbps with UARTCLK at 48 MHz), with fractional baud-rate
generator
5, 6, 7 or 8 bits of data
Even, odd, stick or no-parity bit generation and detection
1 or 2 stop bit generation
Automatic extraction of UART setting for baud rate, character size (7 or 8-bit), parity
configuration and number of stop bits
Support of the modem control functions CTS, RTS (UART0 and UART1), plus DCD,
DSR, RTS, DTS and RI (UART0 only)
Support of software flow control using programmable Xon/Xoff characters
False start bit detection
Line break generation and detection
Separate 8-bit wide, 64-deep transmit FIFO and 12-bit wide, 64-deep receive FIFO
Programmable FIFO disabling for 1-byte depth data path
Receive FIFO trigger levels
The internal register map address space, and the bit function of each register differ
The deltas of the modem status signals are not available
1.5 stop bits is not supported
Independent receive clock feature is not supported
Doc ID 18357 Rev 1
General description
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