MC33988CPNA Freescale, MC33988CPNA Datasheet - Page 13

• Manufacturer Part Number: MC33988CPNA
• Manufacturer: Freescale

Specifications of MC33988CPNA

• Switch Type: High Side
• Power Switch Family: MC33988
• Power Switch On Resistance: 16mOhm
• Output Current: 30A
• Number Of Outputs: Dual
• Mounting: Surface Mount
• Supply Current: 20mA
• Package Type: Power QFN EP
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Pin Count: 16
• Lead Free Status / RoHS Status: Compliant

Table 4. Dynamic Electrical Characteristics (continued)
Analog Integrated Circuit Device Data
Freescale Semiconductor
Typical values noted reflect the approximate parameter mean at T
SPI INTERFACE CHARACTERISTICS
Notes
Recommended Frequency of SPI Operation
Required Low State Duration for
Rising Edge of CS to Falling Edge of CS (Required Setup Time)
Rising Edge of RST to Falling Edge of CS (Required Setup Time)
Falling Edge of
Required High State Duration of SCLK (Required Setup Time)
Required Low State Duration of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of
SI to Falling Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to SI (Required Setup Time)
SO Rise Time
SO Fall Time
SI,
SI,
Time from Falling Edge of
Time from Rising Edge of
Time from Rising Edge of SCLK to SO Data Valid
24.
25.
26.
27.
28.
29.
Characteristics noted under conditions 4.5V ≤ V
C
C
0.2 x V
CS
CS
L
L
= 200pF
= 200pF
, SCLK, Incoming Signal Rise Time
, SCLK, Incoming Signal Fall Time
RST
Maximum setup time required for the 33988 is the minimum guaranteed time needed from the microcontroller.
Rise and Fall time of incoming SI,
Time required for output status data to be available for use at SO. 1.0kΩ on pull-up on
Time required for output status data to be terminated at SO. 1.0kΩ on pull-up on
Time required to obtain valid data out from SO following the rise of SCLK.
DD
low duration measured with outputs enabled and going to OFF or disabled condition.
≤ SO ≤ 0.8 x V
CS
to Rising Edge of SCLK (Required Setup Time)
CS
CS
DD
Characteristic
to SO High-impedance
to SO Low-impedance
, C
RST
L
= 200pF
(24)
CS
CS
(26)
(26)
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
(Required Setup Time)
(29)
(26)
(26)
(27)
(28)
DD
≤ 5.5V, 6.0V ≤ V
(25)
(25)
(25)
(25)
(25)
(25)
A
= 25°C under nominal conditions, unless otherwise noted.
PWR
t
Symbol
t
t
t
SI(HOLD)
t
WSCLKh
t
t
t
t
t
WSCLKl
SO(DIS)
SO(EN)
SI(SU)
t
t
WRST
t
VALID
t
t
f
ENBL
LEAD
t
≤ 27V, -40°C ≤ T
RSO
FSO
LAG
SPI
RSI
RSI
CS
CS
.
CS
DYNAMIC ELECTRICAL CHARACTERISTICS
.
Min
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
A
≤ 125°C, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
Typ
50
50
50
25
25
25
25
65
65
–
–
–
–
–
–
–
–
Max
350
300
167
167
167
167
145
145
105
3.0
5.0
83
83
50
50
50
50
Unit
MHz
ns
ns
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
33988
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