LT1054CSW#TRMPBF Linear Technology, LT1054CSW#TRMPBF Datasheet - Page 6

• Manufacturer Part Number: LT1054CSW#TRMPBF
• Manufacturer: Linear Technology
• Type: Inverting/Step Upr

Specifications of LT1054CSW#TRMPBF

• Operating Supply Voltage (min): 3.5V
• Operating Supply Voltage (max): 15V
• Operating Temp Range: 0C to 100C
• Operating Temperature Classification: Commercial
• Package Type: SOIC W
• Pin Count: 16
• Mounting: Surface Mount
• Output Voltage: AdjV
• Output Current: 100mA
• Lead Free Status / RoHS Status: Compliant

PIN
LT1054/LT1054L
6
from being pulled above the ground pin (Pin 3) during
start-up. Any small, general purpose transistor such as
2N2222 or 2N2219 can be used. R
provide enough base drive to the external transistor so that
it is saturated under nominal output voltage and maximum
output current conditions. In some cases an N-channel
enhancement mode MOSFET can be used in place of the
transistor.
C
V
reference point for use in LT1054-based regulator circuits.
The temperature coefficient of the reference voltage has
been adjusted so that the temperature coefficient of the
regulated output voltage is close to zero. This requires the
reference output to have a positive temperature coefficient
as can be seen in the typical performance curves. This
nonzero drift is necessary to offset a drift term inherent in
the internal reference divider and comparator network tied
to the feedback pin. The overall result of these drift terms
is a regulated output which has a slight positive tempera-
ture coefficient at output voltages below 5V and a slight
negative TC at output voltages above 5V. Reference output
current should be limited, for regulator feedback networks,
to approximately 60 A. The reference pin will draw
internal reference/regulator, so that this pin can also be
used as a pull-up for LT1054 circuits that require synchro-
nization.
IN
REF
100 A when shorted to ground and will not affect the
+
U
R
X
(Pin 6): Reference Output. This pin provides a 2.5V
FUNCTIONS
(
FB/SHDN
CAP
GND
CAP
|
U
V
LT1054
I
OUT
+
–
OUT
V
V
OSC
|
OUT
REF
)
V
+
U
Figure 1
R
X
LOAD
+
V
+
I
C
X
L
OUT
should be chosen to
+
–
I
Q
LT1054 • F01
I
OUT
OSC (Pin 7): Oscillator Pin. This pin can be used to raise or
lower the oscillator frequency or to synchronize the device
to an external clock. Internally Pin 7 is connected to the
oscillator timing capacitor (C
charged and discharged by current sources of 7 A so that
the duty cycle is 50%. The LT1054 oscillator is designed
to run in the frequency band where switching losses are
minimized. However the frequency can be raised, lowered,
or synchronized to an external system clock if necessary.
The frequency can be lowered by adding an external
capacitor (C1, Figure 2) from Pin 7 to ground. This will
increase the charge and discharge times which lowers the
oscillator frequency. The frequency can be increased by
adding an external capacitor (C2, Figure 2, in the range of
5pF to 20pF) from Pin 2 to Pin 7. This capacitor will couple
charge into C
the charge and discharge time, raising the oscillator fre-
quency. Synchronization can be accomplished by adding
an external resistive pull-up from Pin 7 to the reference pin
(Pin 6). A 20k pull-up is recommended. An open collector
gate or an NPN transistor can then be used to drive the
oscillator pin at the external clock frequency as shown in
Figure 2. Pulling up Pin 7 to an external voltage is
not recommended. For circuits that require both fre-
quency synchronization and regulation, an external refer-
ence can be used as the reference point for the top of the
R1/R2 divider allowing Pin 6 to be used as a pull-up point
for Pin 7.
V
C
the input supply and then transfers charge to C
C
IN
IN
+
(Pin 8): Input Supply. The LT1054 alternately charges
to the input voltage when C
is switched in parallel with C
+
C
IN
T
at the switch transitions, which will shorten
FB/SHDN
CAP
GND
CAP
LT1054
+
–
V
V
OSC
OUT
REF
V
Figure 2
+
t
V
IN
IN
+
150pF) which is alternately
is switched in parallel with
OUT
C
OUT
. Switching occurs at
C2
C1
LT1054 • F02
OUT
when
1054lfe