CY7C65113-SXC Cypress Semiconductor Corp, CY7C65113-SXC Datasheet - Page 34

• Manufacturer Part Number: CY7C65113-SXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SXC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Document #: 38-08002 Rev. *D
Table 16-2. Control Bit Definition for Upstream Port
Bit 3: Bus Activity.
Bits 4 and 5: D– Upstream and D+ Upstream.
Bit 6: Endpoint Mode.
Bit 7: Endpoint Size.
The hub generates an EOP at EOF1 in accordance with the USB 1.1 Specification, Section 11.2.2 as well as USB 2.0 specification
(section 11.2.5, page 304).
17.0
The CY7C65113C SIE supports operation as a single device or a compound device. This section describes the two device
addresses, the configurable endpoints, and the endpoint function.
17.1
The USB Controller provides two USB Device Address Registers: A (addressed at 0x10)and B (addressed at 0x40). Upon reset
and under default conditions, Device A has three endpoints and Device B has two endpoints. The USB Device Address Register
contents are cleared during a reset, setting the USB device addresses to zero and disabling these addresses. Figure 17-1 shows
the format of the USB Address Registers.
Bits[6..0]: Device Address.
Bit 7: Device Address Enable.
17.2
The CY7C65113C controller supports up to two addresses and five endpoints for communication with the host. The configuration
of these endpoints, and associated FIFOs, is controlled by bits [7,6] of the USB Status and Control Register (Figure 16-10). Bit
7 controls the size of the endpoints and bit 6 controls the number of addresses. These configuration options are detailed in
Table 17-1. Endpoint FIFOs are part of user RAM (as shown in Section 5.4.1).
USB Device Address (Device A, B)
Bit #
Bit Name
Read/Write
Reset
Control Bits
This is a “sticky” bit that indicates if any non-idle USB event has occurred on the upstream USB port. Firmware should
check and clear this bit periodically to detect any loss of bus activity. Writing a ‘0’ to the Bus Activity bit clears it, while writing
a ‘1’ preserves the current value. In other words, the firmware can clear the Bus Activity bit, but only the SIE can set it.
These bits give the state of each upstream port pin individually: 1 = HIGH, 0 = LOW.
This bit used to configure the number of USB endpoints. See Section 17.2 for a detailed description.
This bit used to configure the number of USB endpoints. See Section 17.2 for a detailed description.
Firmware writes this bits during the USB enumeration process to the non-zero address assigned by the USB host.
Must be set by firmware before the SIE can respond to USB traffic to the Device Address.
000
001
010
100
101
011
110
111
USB Device Addresses
USB Device Endpoints
USB Serial Interface Engine Operation
Address
Enable
Device
Not Forcing (SIE Controls Driver)
Force D+[0] HIGH, D–[0] LOW
Force D+[0] LOW, D–[0] HIGH
Force SE0; D+[0] LOW, D–[0] LOW
Force D+[0] LOW, D–[0] LOW
Force D+[0] HiZ, D–[0] LOW
Force D+[0] LOW, D–[0] HiZ
Force D+[0] HiZ, D–[0] HiZ
R/W
7
0
Address
Device
Bit 6
R/W
6
0
Control Action
Figure 17-1. USB Device Address Registers
Address
Device
Bit 5
R/W
5
0
Address
Device
Bit 4
R/W
4
0
Address
Device
Bit 3
R/W
3
0
Address
Device
Bit 2
R/W
2
0
Addresses 0x10(A) and 0x40(B)
Address
Device
Bit 1
R/W
CY7C65113C
1
0
Page 34 of 49
Address
Device
Bit 0
R/W
0
0