CY7C65113-SXC Cypress Semiconductor Corp, CY7C65113-SXC Datasheet - Page 24

• Manufacturer Part Number: CY7C65113-SXC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113-SXC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Package Type: SOIC
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

Document #: 38-08002 Rev. *D
14.0
Interrupts are generated by GPIO pins, internal timers, I
All interrupts are maskable by the Global Interrupt Enable Register and the USB End Point Interrupt Enable Register. Writing a
‘1’ to a bit position enables the interrupt associated with that bit position.
Bit 0 : USB Bus RST Interrupt Enable
Bit 1 :128-µs Interrupt Enable
Bit 2 : 1.024-ms Interrupt Enable
Bit 3 : USB Hub Interrupt Enable
Bit 4 : Reserved.
Bit 5 : GPIO Interrupt Enable
Bit 6 : I
Bit 7 : Reserved.
Bit 0: EPA0 Interrupt Enable
Bit 1: EPA1 Interrupt Enable
Bit 2: EPA2 Interrupt Enable
Bit 3: EPB0 Interrupt Enable
Bit 4: EPB1 Interrupt Enable
Bit [7..5] : Reserved
USB Endpoint Interrupt Enable
Bit #
Bit Name
Read/Write
Reset
Global Interrupt Enable Register
Bit #
Bit Name
Read/Write
Reset
1 = Enable Interrupt on a USB Bus Reset; 0 = Disable interrupt on a USB Bus Reset (Refer to section 14.3).
1 = Enable Timer interrupt every 128 µs; 0 = Disable Timer Interrupt for every 128 µs.
1 = Enable Timer interrupt every 1.024 ms; 0 = Disable Timer Interrupt every 1.024 ms.
1 = Enable Interrupt on a Hub status change; 0 = Disable interrupt due to hub status change. (Refer to section 14.6.)
1 = Enable Interrupt on falling/rising edge on any GPIO; 0 = Disable Interrupt on falling/rising edge on any GPIO (Refer to
section 14.7, 9.1 and 9.2.).
1 = Enable Interrupt on I2C related activity; 0 = Disable I2C related activity interrupt. (Refer to section 14.8.)
1 = Enable Interrupt on data activity through endpoint A0; 0 = Disable Interrupt on data activity through endpoint A0
1 = Enable Interrupt on data activity through endpoint A1; 0 = Disable Interrupt on data activity through endpoint A1
1 = Enable Interrupt on data activity through endpoint A2; 0 = Disable Interrupt on data activity through endpoint A2.
1 = Enable Interrupt on data activity through endpoint B0; 0 = Disable Interrupt on data activity through endpoint B0
1 = Enable Interrupt on data activity through endpoint B1; 0 = Disable Interrupt on data activity through endpoint B1
2
C Interrupt Enable
Interrupts
Reserved
Reserved
7
–
–
7
–
–
I
2
Reserved
C Interrupt
Enable
R/W
6
0
6
–
–
Figure 14-2. USB Endpoint Interrupt Enable Register
Figure 14-1. Global Interrupt Enable Register
Reserved
Interrupt
Enable
GPIO
R/W
5
0
5
–
–
2
C-compatible operation, internal USB hub and USB traffic conditions.
Reserved
Interrupt
Enable
EPB1
R/W
X
4
4
0
-
USB Hub
Interrupt
Interrupt
Enable
Enable
EPB0
R/W
R/W
3
0
3
0
1.024-ms
Interrupt
Interrupt
Enable
Enable
EPA2
R/W
R/W
2
0
2
0
Interrupt
Interrupt
Enable
128-µs
Enable
EPA1
R/W
CY7C65113C
R/W
1
0
Address 0X20
1
0
Address 0X21
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USB Bus
Interrupt
Interrupt
Enable
Enable
EPA0
RST
R/W
R/W
0
0
0
0