ISP1160BD-S NXP Semiconductors, ISP1160BD-S Datasheet - Page 8

• Manufacturer Part Number: ISP1160BD-S
• Manufacturer: NXP Semiconductors

Specifications of ISP1160BD-S

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Compliant

7. Functional description
8. Microprocessor bus interface
ISP1160-01_7
Product data sheet
7.1 PLL clock multiplier
7.2 Bit clock recovery
7.3 Analog transceivers
7.4 ST-Ericsson Serial Interface Engine (SIE)
8.1 Programmed I/O (PIO) addressing mode
A 6 MHz to 48 MHz clock multiplier Phase-Locked Loop (PLL) is integrated on-chip. This
allows for the use of a low-cost 6 MHz crystal, which also minimizes EMI. No external
components are required for the operation of the PLL.
The bit clock recovery circuit recovers the clock from the incoming USB data stream by
using a 4 times oversampling principle. It is able to track jitter and frequency drift as
specified in Universal Serial Bus Specification Rev. 2.0.
Two sets of transceivers are embedded in the chip for downstream ports with USB
connector type A. The integrated transceivers are compliant with the Universal Serial Bus
Specification Rev. 2.0. These transceivers interface directly with the USB connectors and
cables through external termination resistors.
The ST-Ericsson SIE implements the full USB protocol layer. It is completely hardwired for
speed and needs no firmware intervention. The functions of this block include:
synchronization pattern recognition, parallel to serial conversion, bit (de)stuffing, CRC
checking and generation, Packet IDentifier (PID) verification and generation, address
recognition, and handshake evaluation and generation.
A generic PIO interface is defined for speed and ease-of-use. It also allows direct
interfacing to most microcontrollers. To a microcontroller, the ISP1160/01 appears as a
memory device with a 16-bit data bus and uses the A0 address line to access internal
control registers and FIFO buffer RAM. Therefore, the ISP1160/01 occupies only two
I/O ports or two memory locations of a microprocessor. External microprocessors can
read from or write to the ISP1160/01’s internal control registers and FIFO buffer RAM
through the Programmed I/O (PIO) operating mode.
interface between a microprocessor and the ISP1160/01.
Rev. 07 — 29 September 2009
Figure 3
Embedded USB host controller
shows the Programmed I/O
ISP1160/01
© ST-ERICSSON 2009. All rights reserved.
8 of 87