ISP1581BD NXP Semiconductors, ISP1581BD Datasheet - Page 20

• Manufacturer Part Number: ISP1581BD
• Manufacturer: NXP Semiconductors

Specifications of ISP1581BD

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
Table 7:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
Mode register: bit allocation
CLKAON
R/W
7
0
0
9.2.2 Mode register (address: 0CH)
9.2.3 Interrupt Configuration register (address: 10H)
This register consists of 1 byte (bit allocation: see
upper byte is ignored.
The Mode register controls the resume, suspend and wake-up behavior, interrupt
activity, soft reset, clock signals and SoftConnect operation.
SNDRSU
Table 8:
This 1-byte register determines the behavior and polarity of the INT output. The bit
allocation is shown in
or STALL, it will generate interrupts depending on three Debug mode bit fields:
Bit
7
6
5
4
3
2
1
0
•
•
R/W
CDBGMOD[1:0]: interrupts for the Control endpoint 0
DDBGMODIN[1:0]: interrupts for the DATA IN endpoints 1 to 7
6
0
0
Mode register: bit description
Symbol
CLKAON
SNDRSU
GOSUSP
SFRESET
GLINTENA
WKUPCS
-
SOFTCT
GOSUSP
R/W
5
0
0
Rev. 06 — 23 December 2004
Table
SFRESET
Description
Clock Always On: A logic 1 indicates that the internal clocks
are always running even during ‘suspend’ state. A logic 0
switches off the internal oscillator and PLL, when they are not
needed. During ‘suspend’ state, this bit must be set to logic 0 to
meet the suspend current requirements. The clock is stopped
after a delay of approximately 2 ms, following the setting of bit
GOSUSP.
Send Resume: Writing a logic 1 followed by a logic 0 will
generate an upstream ‘resume’ signal of 10 ms duration, after a
5 ms delay.
Go Suspend: Writing a logic 1 followed by a logic 0 will activate
‘suspend’ mode.
Soft Reset: Writing a logic 1 followed by a logic 0 will enable a
software-initiated reset to ISP1581. A soft reset is similar to a
hardware-initiated reset (via the RESET pin).
Global Interrupt Enable: A logic 1 enables all interrupts.
Individual interrupts can be masked OFF by clearing the
corresponding bits in the Interrupt Enable register. Bus reset
value: unchanged.
Wake-up on Chip Select: A logic 1 enables remote wake-up
via a LOW level on input CS.
reserved; must write logic 0
SoftConnect: A logic 1 enables the connection of the 1.5 k
pull-up resistor on pin RPU to the D line. Bus reset value:
unchanged.
R/W
9. When the USB SIE receives or generates a ACK, NAK
4
0
0
GLINTENA
unchanged
R/W
3
0
Hi-Speed USB peripheral controller
WKUPCS
Table
R/W
2
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7). In 16-bit bus mode the
reserved
1
-
-
-
ISP1581
unchanged
SOFTCT
R/W
0
0
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