PSD834F2-15M STMicroelectronics, PSD834F2-15M Datasheet - Page 54
PSD834F2-15M
Manufacturer Part Number
PSD834F2-15M
Description
Manufacturer
STMicroelectronics
Datasheet
1.PSD834F2-15M.pdf
(95 pages)
Specifications of PSD834F2-15M
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Package Type
PQFP
Mounting
Surface Mount
Pin Count
52
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
PSD834F2V
Port D – Functionality and Structure
Port D has three I/O pins. See Figure 26 and Fig-
ure 27. This port does not support Address Out
mode, and therefore no Control Register is re-
quired. Port D can be configured to perform one or
more of the following functions:
■
■
■
Figure 26. Port D Structure
54/95
MCU I/O Mode
CPLD Output – External Chip Select (ECS0-
ECS2)
CPLD Input – direct input to the CPLD, no Input
Macrocells (IMC)
ECS [ 2:0 ]
WR
WR
READ MUX
DATA OUT
DIR REG.
D
D
REG.
P
D
B
Q
Q
DATA OUT
DATA IN
■
Port D pins can be configured in PSDsoft Express
as input pins for other dedicated functions:
■
■
■
Slew rate – pins can be set up for fast slew rate
Address Strobe (ALE/AS, PD0)
CLKIN (PD1) as input to the macrocells flip-
flops and APD counter
PSD Chip Select Input (CSI, PD2). Driving this
signal High disables the Flash memory, SRAM
and CSIOP.
CPLD- INPUT
OUTPUT
OUTPUT
SELECT
MUX
ENABLE PRODUCT
TERM (.OE)
PORT D PIN
AI02889