ISP1160BM/01 STEricsson, ISP1160BM/01 Datasheet - Page 77

• Manufacturer Part Number: ISP1160BM/01
• Manufacturer: STEricsson

Specifications of ISP1160BM/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

18. Application information
ISP1160-01_7
Product data sheet
Fig 40. Typical interface circuit to Hitachi SH-3 (SH7709) RISC processor.
CLKOUT
+ 5 V
+ 3.3 V
kHz
For MOSFET, R
32
+ 3.3 V
+ 5 V
EXTAL
XTAL
EXTAL2
XTAL2
GND
18.1 Typical interface circuit
18.2 Interfacing a ISP1160/01 to a SH7709 RISC processor
SH7709
RD/WR_N
DACK0_N
RSTOUT
DREQ0
D [ 15:0 ]
RD_N
PTC0
PTC1
IRQ2
DSon
CS5
This section shows a typical interface circuit between the ISP1160/01 and a RISC
processor. The Hitachi SH-3 series RISC processor SH7709 is used as the example. The
main ISP1160/01 signals to be taken into consideration for connecting to a SH7709 RISC
processor are:
A1
•
•
•
•
= 150 mΩ.
A 16-bit data bus: D[15:0] for the ISP1160/01. The ISP1160/01 is ‘little endian’
compatible.
The address line A0 is needed for a complete addressing of the ISP1160/01 internal
registers:
– A0 = 0 will select the Data Port of the Host Controller
– A0 = 1 will select the Command Port of the Host Controller
The CS_N line is used for chip selection of the ISP1160/01 in a certain address range
of the RISC system. This signal is active LOW.
RD_N and WR_N are common read and write signals. These signals are active LOW.
+ 5 V
7
D [ 15:0 ]
A0
CS_N
RD_N
WR_N
DREQ
DACK_N
EOT
INT
H_WAKEUP
H_SUSPEND
RESET_N
DGND
AGND
ISP1160/01
H_PSW2_N
H_PSW1_N
V REG(3V3)
H_OC1_N
H_OC2_N
NDP_SEL
Rev. 07 — 29 September 2009
V HOLD1
V HOLD2
H_DM1
H_DM2
H_DP1
H_DP2
XTAL2
XTAL1
V CC
22 pF
V DD
V reg
004aaa072
6 MHz
+ 3.3 V
V DD
+ 5 V
22 pF
+ 3.3 V
+ 5 V
Embedded USB host controller
22 Ω
22 Ω
(2×)
(2×)
47 pF
47 pF
(2×)
(2×)
MOSFET
ISP1160/01
(2×)
Vbus_DN2 Vbus_DN1
© ST-ERICSSON 2009. All rights reserved.
FB3
FB1
FB2
FB4
downstream
downstream
port #1
port #2
USB
USB
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