ISP1160BM/01 STEricsson, ISP1160BM/01 Datasheet - Page 42

• Manufacturer Part Number: ISP1160BM/01
• Manufacturer: STEricsson

Specifications of ISP1160BM/01

• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 18.
ISP1160-01_7
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcInterruptDisable register: bit allocation
10.1.6 HcInterruptDisable register (R/W: 05H/85H)
reserved
R/W
R/W
R/W
R/W
MIE
31
23
15
0
0
0
7
0
Table 17.
Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt
bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the
HcInterruptEnable register. Thus, writing a logic 1 to a bit in this register clears the
corresponding bit in the HcInterruptEnable register, whereas writing a logic 0 to a bit in
this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On
a read, the current value of the HcInterruptEnable register is returned.
Code (Hex): 05 — read
Code (Hex): 85 — write
Table 19.
Bit
2
1
0
Bit
31
30 to 7
6
RHSC
R/W
R/W
R/W
R/W
30
22
14
0
0
0
6
0
HcInterruptEnable register: bit description
HcInterruptDisable register: bit description
Symbol
SF
-
SO
Symbol
MIE
-
RHSC
FNO
R/W
R/W
R/W
R/W
29
21
13
0
0
0
5
0
Rev. 07 — 29 September 2009
Description
0 — ignore
1 — enable interrupt generation due to Start of frame
reserved
0 — ignore
1 — enable interrupt generation due to Scheduling Overrun
Description
A logic 0 is ignored by the HC. A logic 1 disables interrupt generation
due to events specified in other bits of this register. This field is set
after a hardware or software reset.
reserved
0 — ignore
1 — disable interrupt generation due to Root Hub Status Change
R/W
R/W
R/W
R/W
UE
28
20
12
0
0
0
4
0
reserved
reserved
reserved
R/W
R/W
R/W
R/W
RD
27
19
11
0
0
0
3
0
…continued
Embedded USB host controller
R/W
R/W
R/W
R/W
SF
26
18
10
0
0
0
2
0
ISP1160/01
reserved
© ST-ERICSSON 2009. All rights reserved.
R/W
R/W
R/W
R/W
25
17
0
0
9
0
1
0
R/W
R/W
R/W
R/W
SO
24
16
0
0
8
0
0
0
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