ISP1181ADGG STEricsson, ISP1181ADGG Datasheet - Page 30
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ISP1181ADGG
Manufacturer Part Number
ISP1181ADGG
Description
Manufacturer
STEricsson
Datasheet
1.ISP1181ADGG.pdf
(71 pages)
Specifications of ISP1181ADGG
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Philips Semiconductors
Table 22:
9397 750 13959
Product data
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
Interrupt Enable Register: bit allocation
IEP14
IEP6
R/W
R/W
R/W
31
23
15
0
0
0
12.1.5 Write/Read Interrupt Enable Register
Table 21:
This command is used to individually enable/disable interrupts from all endpoints, as
well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend,
resume, reset). A bus reset will not change any of the programmed bit values.
The command accesses the Interrupt Enable Register, which consists of 4 bytes. The
bit allocation is given in
Code (Hex): C2/C3 — write/read Interrupt Enable Register
Transaction — write/read 4 bytes
Bit
6
5
4
3
2
1
0
IEP13
IEP5
R/W
R/W
R/W
30
22
14
0
0
0
Hardware Configuration Register: bit description
Symbol
DRQPOL
DAKPOL
EOTPOL
WKUPCS
PWROFF
INTLVL
INTPOL
IEP12
IEP4
R/W
R/W
R/W
29
21
13
0
0
0
Rev. 05 — 08 December 2004
Table
IEP11
Description
Selects DREQ signal polarity (0 = active LOW, 1 = active
HIGH). Bus reset value: unchanged.
Selects DACK signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
Selects EOT signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
A logic 1 enables remote wake-up via a LOW level on input CS
(For wake-up on CS to work, V
Bus reset value: unchanged.
A logic 1 enables powering-off during ‘suspend’ state. Output
SUSPEND is configured as a power switch control signal for
external devices (HIGH during ‘suspend’). This value should
always be initialized to logic 1. Bus reset value: unchanged.
Selects the interrupt signalling mode on output INT (0 = level,
1 = pulsed). In pulsed mode an interrupt produces an 166 ns
pulse. See
Selects INT signal polarity (0 = active LOW, 1 = active HIGH).
Bus reset value: unchanged.
IEP3
R/W
R/W
R/W
28
20
12
0
0
0
22.
reserved
Section 13
IEP10
IEP2
R/W
R/W
R/W
27
19
11
0
0
0
Full-speed USB peripheral controller
for details. Bus reset value: unchanged.
IEP9
IEP1
R/W
R/W
R/W
26
18
10
0
0
0
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
BUS
must be present.).
…continued
IEP0IN
IEP8
ISP1181A
R/W
R/W
R/W
25
17
0
0
9
0
IEP0OUT
IEP7
R/W
R/W
R/W
24
16
0
0
8
0
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