W83697HG-TR Nuvoton Technology Corporation of America, W83697HG-TR Datasheet - Page 74

• Manufacturer Part Number: W83697HG-TR
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of W83697HG-TR

• Lead Free Status / RoHS Status: Supplier Unconfirmed

CRF1 (Default 0x00)
Bit 4: Swap Drive 0, 1 Mode
Bit 3 - 2 Interface Mode
Bit 1: FDC DMA Mode
Bit 0: Floppy Mode
Bit 7 - 6: Boot Floppy
Bit 5, 4: Media ID1, Media ID0. These bits will be reflected on FDC's Tape Drive Register bit 7, 6.
Bit 3 - 2: Density Select
Bit 1: DISFDDWR
Bit 0: SWWP
= 0
= 1
= 11
= 10 (Reserved)
= 01 PS/2
= 00 Model 30
= 0 Burst Mode is enabled
= 1 Non-Burst Mode (Default)
= 0 Normal Floppy Mode (Default)
= 1 Enhanced 3-mode FDD
= 00 FDD A
= 01 FDD B
= 10 FDD C
= 11 FDD D
= 00 Normal (Default)
= 01 Normal
= 10 1 ( Forced to logic 1)
= 11 0 ( Forced to logic 0)
= 0 Enable FDD write.
= 1 Disable FDD write(forces pins WE, WD stay high).
= 0 Normal, use WP to determine whether the FDD is write protected or not.
= 1 FDD is always write-protected.
No Swap (Default)
Drive and Motor select 0 and 1 are swapped.
AT Mode (Default)
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Publication Release Date: May 30, 2005
W83697HF/ HG
Revision A1