CY7C63723-SCT Cypress Semiconductor Corp, CY7C63723-SCT Datasheet - Page 29

• Manufacturer Part Number: CY7C63723-SCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63723-SCT

• Lead Free Status / RoHS Status: Not Compliant

Processor Status and Control Register
Bit 7: IRQ Pending
Bit 6: Watchdog Reset
Bit 5: Bus Interrupt Event
Bit 4: LVR/BOR Reset
Document #: 38-08022 Rev. *D
When an interrupt is generated, it is registered as a pending
interrupt. The interrupt will remain pending until its interrupt
enable bit is set (Figure and Figure ) and interrupts are glo-
bally enabled (Bit 2, Processor Status and Control Register).
At that point the internal interrupt handling sequence will clear
the IRQ Pending bit until another interrupt is detected as
pending. This bit is only valid if the Global Interrupt Enable bit
is disabled.
1 = There are pending interrupts.
0 = No pending interrupts.
The Watchdog Timer Reset (WDR) occurs when the internal
Watchdog timer rolls over. The timer will roll over and WDR
will occur if it is not cleared within t
value of t
a Watchdog reset can occur with a POR/LVR/BOR event, as
discussed at the end of this section.
1 = A Watchdog reset occurs.
0 = No Watchdog reset
The Bus Reset Status is set whenever the event for the USB
Bus Reset or PS/2 Activity interrupt occurs. The event type
(USB or PS/2) is selected by the state of the USB-PS/2 Inter-
rupt Mode bit in the USB Status and Control Register (see
Figure 14). The details on the event conditions that set this bit
are given in Section . In either mode, this bit is set as soon as
the event has lasted for 128–256 μs, and the bit will be set
even if the interrupt is not enabled. The bit is only cleared by
firmware or LVR/WDR.
1 = A USB reset occurred or PS/2 Activity is detected, de-
pending on USB-PS/2 Interrupt Select bit.
0 = No event detected since last cleared by firmware or
LVR/WDR.
The Low-voltage or Brown-out Reset is set to ‘1’ during a
power-on reset. Firmware can check bits 4 and 6 in the reset
handler to determine whether a reset was caused by a
LVR/BOR condition or a Watchdog timeout. This bit is not
Read/Write
Bit Name
Reset
Bit #
WATCH
). This bit is cleared by an LVR/BOR. Note that
Pending
IRQ
R
7
0
Figure 33. Processor Status and Control Register (Address 0xFF)
Watchdog
Reset
R/W
WATCH
6
1
(see Section for the
Interrupt
Event
R/W
Bus
5
0
LVR/BOR
Reset
R/W
4
1
Bit 3: Suspend
Bit 2: Interrupt Enable Sense
Bit 1: Reserved. Must be written as a 0.
Bit 0: Run
affected by WDR. Note that a LVR/BOR event may be fol-
lowed by a Watchdog reset before firmware begins executing,
as explained at the end of this section.
1 = A POR or LVR has occurred.
0 = No POR nor LVR since this bit last cleared.
Writing a '1' to the Suspend bit will halt the processor and
cause the microcontroller to enter the suspend mode that sig-
nificantly reduces power consumption. An interrupt or USB
bus activity will cause the device to come out of suspend.
After coming out of suspend, the device will resume firmware
execution at the instruction following the IOWR which put the
part into suspend. When writing the suspend bit with a resume
condition present (such as non-idle USB activity), the sus-
pend state will still be entered, followed immediately by the
wake-up process (with appropriate delays for the clock
start-up). See Section for more details on suspend mode
operation.
1 = Suspend the processor.
0 = Not in suspend mode. Cleared by the hardware when
resuming from suspend.
This bit shows whether interrupts are enabled or disabled.
Firmware has no direct control over this bit as writing a zero
or one to this bit position will have no effect on interrupts. This
bit is further gated with the bit settings of the Global Interrupt
Enable Register (Figure ) and USB Endpoint Interrupt Enable
Register (Figure ). Instructions DI, EI, and RETI manipulate
the state of this bit.
1 = Interrupts are enabled.
0 = Interrupts are masked off.
This bit is manipulated by the HALT instruction. When Halt is
executed, the processor clears the run bit and halts at the end
of the current instruction. The processor remains halted until
a reset occurs (low-voltage, brown-out, or Watchdog). This bit
should normally be written as a ‘1’.
Suspend
R/W
3
0
Interrupt
Enable
Sense
R
2
0
Reserved
1
0
-
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CY7C63723C
CY7C63743C
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R/W
Run
0
1
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