CY7C63723-SCT Cypress Semiconductor Corp, CY7C63723-SCT Datasheet - Page 28

• Manufacturer Part Number: CY7C63723-SCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C63723-SCT

• Lead Free Status / RoHS Status: Not Compliant

Bit 7: First Edge Hold
Bit [6:4]: Prescale Bit [2:0]
Bit [3:0]: Capture A/B, Rising/Falling Interrupt Enable
Document #: 38-08022 Rev. *D
1 = The time of the first occurrence of an edge is held in the
Capture Timer Data Register until the data is read. Subse-
quent edges are ignored until the Capture Timer Data Regis-
ter is read.
0 = The time of the most recent edge is held in the Capture
Timer Data Register. That is, if multiple edges have occurred
before reading the capture timer, the time for the last one will
be read (default state).
The First Edge Hold function applies globally to all four cap-
ture timers.
Three prescaler bits allow the capture timer clock rate to be
selected among 5 choices, as shown in
Each of the four Capture Timer registers can be individually
enabled to provide interrupts.
Table 6
below.
Table 6. Capture Timer Prescalar Settings (Step size and
range for F
Prescale
Both Capture A events share a common interrupt request, as
do the two Capture B events. In addition to the event enables,
the main Capture Interrupt Enables bit in the Global Interrupt
Enable register (Section ) must be set to activate a capture
interrupt.
1 = Enable interrupt
0 = Disable interrupt
000
001
010
011
100
2:0
Bits 7:0 of free-running timer
Bits 8:1 of free-running timer
Bits 9:2 of free-running timer
Bits 10:3 of free-running timer
Bits 11:4 of free-running timer
CLK
= 6 MHz)
Captured Bits
CY7C63722C
CY7C63723C
CY7C63743C
16 μs 4.096 ms
Step
LSB
Size
1 μs
2 μs
4 μs
8 μs
Page 28 of 53
1.024 ms
2.048 ms
Range
256 μs
512 μs
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