FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 384
FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
Lead Free Status / RoHS Status
Not Compliant
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LPC Interface Bridge Registers (D31:F0)
9.9
9.9.1
9.9.2
384
Table 150. APM Register Map
APM I/O Decode
Table 150
the PCI Device 31: Function 0 space (APMDEC_EN), and cannot be moved (fixed I/O location).
APM_CNT—Advanced Power Management Control Port
Register
I/O Address:
Default Value:
Lockable:
Power Well:
APM_STS—Advanced Power Management Status Port
Register
I/O Address:
Default Value:
Lockable:
Power Well:
Address
Bit
7:0
Bit
7:0
B2h
B3h
Used to pass data between the OS and the SMI handler. Basically, this is a scratchpad register and
is not affected by any other register or function (other than a PCI reset).
Used to pass an APM command between the OS and the SMI handler. Writes to this port not only
store data in the APMC register, but also generate an SMI# when the APMC_EN bit is set.
shows the I/O registers associated with APM support. This register space is enabled in
Mnemonic
APM_CNT
APM_STS
B2h
00h
No
Core
00h
No
Core
B3h
Advanced Power Management Control Port
Advanced Power Management Status Port
Register Name
Intel
Description
Description
Attribute:
Size:
Usage:
Attribute:
Size:
Usage:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/W
8-bit
Legacy Only
R/W
8-bit
Legacy Only
Default
00h
00h
Type
R/W
R/W
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