FW82801ER S L742 Intel, FW82801ER S L742 Datasheet - Page 325
FW82801ER S L742
Manufacturer Part Number
FW82801ER S L742
Description
Manufacturer
Intel
Datasheet
1.FW82801ER_S_L742.pdf
(671 pages)
Specifications of FW82801ER S L742
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9.1.14
9.1.15
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
GPIO_BASE—GPIO Base Address Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
GPIO_CNTL—GPIO Control Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
31:16
15:6
Bit
5:1
Bit
7:5
3:0
0
4
Reserved
Base Address — R/W. This field provides the 64 bytes of I/O space for GPIO.
Reserved
Resource Type Indicator — RO. Hardwired to 1 to indicate I/O space.
Reserved
GPIO Enable (GPIO_EN) — R/W. This bit enables/disables decode of the I/O range pointed to by
the GPIO base register and enables/disables the GPIO function.
0 = Disable
1 = Enable
Reserved
58h
00000001h
No
5Ch
00h
No
–
5Bh
Description
Description
LPC Interface Bridge Registers (D31:F0)
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
R/W, RO
32 bit
Core
R/W
8 bit
Core
325
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