FDC37C665GT-MS Standard Microsystems (SMSC), FDC37C665GT-MS Datasheet - Page 36
FDC37C665GT-MS
Manufacturer Part Number
FDC37C665GT-MS
Description
Manufacturer
Standard Microsystems (SMSC)
Datasheet
1.FDC37C665GT-MS.pdf
(152 pages)
Specifications of FDC37C665GT-MS
Pin Count
100
Lead Free Status / RoHS Status
Compliant
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Quantity
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Part Number:
FDC37C665GT-MS
Manufacturer:
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DIGITAL INPUT REGISTER (DIR)
Address 3F7 READ ONLY
This register is read-only in all modes.
PC-AT Mode
BIT 0 - 6 UNDEFINED
The data bus outputs D0 - 6 will remain in a
high impedance state during a read of this
register.
PS/2 Mode
BIT 0 nHIGH DENS
This bit is low whenever the 500 Kbps or 1 Mbps
data rates are selected, and high when 250Kbps
and 300Kbps are selected.
BITS 1 - 2 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
corresponding to the individual data rates. The
data rate select bits are
RESET
COND.
RESET
COND.
See Table 13 for the settings
CHG
DSK
CHG
N/A
DSK
N/A
7
7
unaffected
N/A
N/A
6
1
6
N/A
N/A
5
1
5
by
a
N/A
36
N/A
4
1
4
BIT 7 DSKCHG
This bit monitors the pin of the same name and
reflects the opposite value seen on the disk
cable.
software reset, and are set to 250kb/s after a
hardware reset.
BITS 3 - 6 UNDEFINED
Always read as a logic "1"
BIT 7 DSKCHG
This bit monitors the pin of the same name and
reflects the opposite value seen on the disk
cable.
N/A
N/A
3
1
3
DRATE
SEL1
N/A
N/A
2
2
DRATE
SEL0
N/A
N/A
1
1
nHIGH
DENS
N/A
0
1
0
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