HDSP2114S OSRAM Opto Semiconductors Inc, HDSP2114S Datasheet - Page 10

• Manufacturer Part Number: HDSP2114S
• Description: LED Displays 5x7 Hi-Eff Green 0.2 , 8-CHARACTER
• Manufacturer: OSRAM Opto Semiconductors Inc
• Series: Intelligent Display®r

Specifications of HDSP2114S

• Display Type: Dot Matrix
• Emitting Color: Hi-Eff. Green
• Number Of Digits: 8
• Digit Size (in): .2in
• Viewing Area Height (mm): 4.81mm
• Viewing Area Length (mm): 2.85mm
• Package Type: Panel
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Operating Temp Range: -40C to 85C
• Mounting: Through Hole
• Pin Count: 28
• Total Thickness (mm): 5.31mm
• Opto Display Type: Panel
• Pattern Type: Dot Matrix
• Millicandela Rating: 200µcd
• Size / Dimension: 1.70" L x 0.77" W x 0.21" H (42.67mm x 19.58mm x 5.31mm)
• Color: Green
• Configuration: 5 x 7
• Character Size: 0.2 in
• Illumination Color: High Efficiency Green
• Wavelength: 568 nm
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Luminous Intensity: 510 ucd
• Viewing Area (w X H): 2.85 mm x 4.81 mm
• Lead Free Status / RoHS Status: Compliant
• Voltage - Forward (vf) Typ: -
• Internal Connection: -
• Lead Free Status / Rohs Status: Details
• Other names: Q68000A8564

Memory Selection
FL
0
1
1
1
1
Theory of operation
The HDSP211XS Programmable Display is designed to work with
all major microprocessors. Data entry is via an eight bit parallel
bus. Three bits of address route the data to the proper digit loca-
tion in the RAM. Standard control signals like WR and CE allow
the data to be written into the display.
D0–D7 data bits are used for both Character RAM and control
word data input. A3 acts as the mode selector.
If A3=1, character RAM is selected. Then input data bit D7 will
determine whether input data bits D0–D6 is ASCII coded data
(D7=0) or UDC data (D7=1). See section on UDC Address Regis-
ter and RAM.
For normal operation FL pin should be held high. When FL is held
low, Flash RAM is accessed to set character blinking.
The seven bit ASCII code is decoded by the Character ROM to
generate Column data. Twenty columns worth of data is sent out
each display cycle, and it takes fourteen display cycles to write into
eight digits.
The rows are multiplexed in two sets of seven rows each. The
internal timing and control logic synchronizes the turning on of
rows and presentation of column data to assure proper display
operation.
Power Up Sequence
Upon power up display will come on at random. Thus the display
should be reset on power-up. The reset will clear the Flash RAM,
Control Word Register and reset the internal counter. All the dig-
its will show blanks and display brightness level will be 100%.
The display must not be accessed until three clock pulses
(110 µseconds minimum using the internal clock) after the rising
edge of the reset line.
Microprocessor interface
The interface to a microprocessor is through the 8-bit data bus
(D0–D7), the 4-bit address bus (A0–A3) and control lines FL , CE
and WR.
To write data (ASCII/Control Word) into the display CE should be
held low, address and data signals stable and WR should be
brought low. The data is written on the low to high transition of
WR.
The Control Word is decoded by the Control Word Decode Logic.
Each code has a different function. The code for display brightness
changes the duty cycle for the column drivers. The peak LED cur-
rent stays the same but the average LED current diminishes
depending on the intensity level.
The character Flash Enable causes 2.0 Hz coming out of the
counter to be ANDED with column drive signal and makes the col-
umn driver to cycle at 2.0 Hz. Thus the character flashes at 2.0 Hz.
2006-01-23
HSDP2110S, HSDP2111S, HSDP2112S, HSDP2113S, HSDP2114S, HSDP2115S
A4
X
0
0
1
1
A3
X
0
1
1
0
Section of Memory
Flash RAM
UDC Address Register
UDC RAM
Character RAM
Control Word Register
A2–A0
Character Address
Don’t Care
Row Address
Character Address
Don’t Care
10
The display Blink works the same way as the Flash Enable but
causes all twenty column drivers to cycle at 2.0 Hz thereby making
all eight digits to blink at 2.0 Hz.
The Self Test function of the IC consists of two internal routines
which exercise major portions of the IC and illuminates all the
LEDs.
Clear bit clears the character RAM and writes a blank into the dis-
play memory. It however does not clear the control word.
ASCII Data or Control Word Data can be written into the display at
this point. For multiple display operation, CLK I/O must be properly
selected. CLK I/O will output the internal clock if CLKSEL=1, or will
allow input from an external clock if CLKSEL=0.
Character RAM
The Character RAM is selected when FL, A4 and A3 are set to
1,1,1 during a read or write cycle. The Character RAM is a 8 by 8
bit RAM with each of the eight locations corresponding to a digit on
the display. Digit 0 is on the left side of the display and digit 7 is on
the right side of the display. Address lines, A2–A0 select the digit
address with A2 being the most significant bit and A0 being the
least significant bit. The two types of data stored in the Character
RAM are the ASCII coded data and the UDC Address Data. The
type of data stored in the Character RAM is determined by data bit,
D7. If D7 is low, then ASCII coded data is stored in data bits D6–
D0. If D7 is high, then UDC Address Data is stored in data bit D3–
D0.
The ASCII coded data is a 7 bit code used to select one of 128
ASCII characters permanently stored in the ASCII ROM.
The UDC Address data is a 4 bit code used to select one of the
UDC characters in the UDC RAM. There are up to 16 characters
available. See Table „Character RAM Access Logic“ (page 11).
UDC Address Register and UDC RAM
The UDC Address Register and UDC RAM allows the user to gen-
erate and store up to 16 custom characters. Each custom charac-
ter is defined in 5 x 7 dot matrix pattern. It takes 8 write cycles to
define a custom character, one cycle to load the UDC Address
Register and 7 cycles to define the character. The contents of the
UDC Address Register will store the 4 bit address for one of the 16
UDC RAM locations. The UDC RAM is used to store the custom
character.
Data Bits Used
D0
D3–D0
D4–D0
D7–D0
D7–D0