AD6624AS Analog Devices Inc, AD6624AS Datasheet - Page 31

• Manufacturer Part Number: AD6624AS
• Manufacturer: Analog Devices Inc

Specifications of AD6624AS

• Lead Free Status / RoHS Status: Not Compliant

high is processed. When these bits are 11, the accumulator and
sample CLK are determined by the rate at which the IEN pin
toggles. The data that is captured on the rising edge of CLK
after IEN transitions from high to low is processed. For example,
Control Modes 10 and 11 can be used to allow interleaved data
from either the A or B Input Ports and then assigned to the respec-
tive channel. The IEN pin selects the data such that a channel
could be configured in Mode 10 and another could be config-
ured in Mode 11.
Bit 3 determines whether or not the phase accumulator of the
NCO is cleared when a Hop occurs. The Hop can originate
from either the Pin_SYNC or Soft_SYNC. When this bit is set
to 0, the Hop is phase continuous and the accumulator is not
cleared. When this bit is set to 1, the accumulator is cleared to 0
before it begins accumulating the new frequency word. This is
appropriate when multiple channels are hopping from different
frequencies to a common frequency.
Bits 2–1 control whether or not the dithers of the NCO are acti-
vated. The use of these features is heavily determined by the
system constraints. Consult the NCO section of the data sheet
for more detailed information on the use of dither.
Bit 0 of this register allows the NCO Frequency translation stage to
be bypassed. When this occurs, the data from the A Input Port
is passed down the I path of the channel and the data from the
B Input Port is passed down the Q path of the channel. This allows
a real filter to be performed on baseband I and Q data.
0x90: rCIC2 Decimation–1 (M
This register is used to set the decimation in the rCIC2 filter. The
value written to this register is the decimation minus one. The
rCIC2 decimation can range from 1 to 4096 depending upon the
interpolation of the channel. The decimation must always be
greater than the interpolation. M
L
Scalar can be chosen. For more details, consult the rCIC2 section.
0x91: rCIC2 Interpolation–1 (L
This register is used to set the interpolation in the rCIC2 filter.
The value written to this register is the interpolation minus one.
The rCIC2 interpolation can range from 1 to 512 depending
upon the decimation of the rCIC2. There is no timing error
associated with this interpolation. See the rCIC2 section of the
data sheet for further details.
0x92: rCIC2 Scale
The rCIC2 scale register is used to provide attenuation to com-
pensate for the gain of the rCIC2 and to adjust the linearization
of the data from the floating-point input. The use of this scale
register is influenced by both the rCIC2 growth and floating-
point input port considerations. The rCIC2 section should be
consulted for details. The rCIC2 scalar has been combined with
the Exponent Offset and will need to be handled appropriately
in both the Input Port and rCIC2 sections.
Bit 11 determines the polarity of the exponent. Normally, this
bit will be cleared unless an ADC such as the AD6600 is used,
in which case, this bit will be set.
Bit 10 determines the weight of the exponent word associated
with the input port. When this bit is low, each exponent step is
considered to be worth 6.02 dB. When this bit is high, each
exponent step is considered to be worth 12.02 dB.
Bits 9–5 are the actual scale values used when the Level Indica-
tor, LI pin associated with this channel is active.
REV. B
rCIC2
and both must be chosen such that a suitable rCIC2
rCIC2
rCIC2
rCIC2
must be chosen larger than
–1)
–1)
–31–
Bits 4–0 are the actual scale values used when the Level Indica-
tor, LI pin associated with this channel is inactive.
0x93:
Reserved. (Must be written low.)
0x94: CIC5 Decimation–1 (M
This register is used to set the decimation in the CIC5 filter.
The value written to this register is the decimation minus one.
Although this is an 8-bit register, the decimation is usually lim-
ited to values between 1 and 32. Decimations higher than 32
would require more scaling than the CIC5’s capability.
0x95: CIC5 Scale
The CIC5 scale factor is used to compensate for the growth of
the CIC5 filter. Consult the CIC5 section for details.
0x96:
Reserved. (Must be written low.)
0xA0: RCF Decimation–1 (M
This register is used to set the decimation of the RCF stage. The
value written is the decimation minus one. Although this is an 8-bit
register that allows decimation up to 256 for most filtering sce-
narios, the decimation should be limited to values between 1 and
32. Higher decimations are allowed, but the alias protection of the
RCF may not be acceptable for some applications.
0xA1: RCF Decimation Phase (P
This register allows any one of the M
be used and can be adjusted dynamically. Each time a filter is
started, this phase is updated. When a channel is synchronized,
it will retain the phase setting chosen here. This can be used as
part of a timing recovery loop with an external processor or can
allow multiple RCFs to work together while using a single RCF
pair. The RCF section of the data sheet should be consulted for
further details.
0xA2: RCF Number of Taps Minus One (N
The number of taps for the RCF filter minus one is written here.
0xA3: RCF Coefficient Offset (CO
This register is used to specify which section of the 256-word
coefficient memory is used for a filter. It can be used to select
among multiple filters that are loaded into memory and refer-
enced by this pointer. This register is shadowed and the filter
pointer is updated every time a new filter is started. This allows
the Coefficient Offset to be written even while a filter is being
computed with disturbing operation. The next sample that
comes out of the RCF will be with the new filter.
0xA4: RCF Control Register
The RCF Control Register is an 11-bit register that controls
general features of the RCF as well as output formatting. The
bits of this register and their functions are described below.
Bit 10 bypasses the RCF filter and sends the CIC5 output data
to the BIST-I and BIST-Q registers. The 16 MSBs of the CIC5
data can be accessed from this register if Bit 9 of the Serial
Control Register at channel address 0xA9 is set.
Bit 9 of this register controls the source of the input data to the
RCF. If this bit is 0, the RCF processes the output data of its
own channel. If this bit is 1, it processes the data from the CIC5
of another channel. The CIC5 that the RCF is connected to
when this bit is 1 is shown in Table IX. This can be used to
allow multiple RCFs to be used together to process wider
bandwidth channels. See the Multiprocessing section of the data
sheet for further details.
RCF
CIC5
–1)
–1)
RCF
RCF
RCF
)
)
phases of the filter to
RCF
AD6624
–1)