AD6624AS Analog Devices Inc, AD6624AS Datasheet - Page 26

• Manufacturer Part Number: AD6624AS
• Manufacturer: Analog Devices Inc

Specifications of AD6624AS

• Lead Free Status / RoHS Status: Not Compliant

AD6624
Serial Ports Cascaded
Serial output ports may be cascaded on the AD6624 such that
the SDO’s outputs are shorted together. In this mode, the SDO
port of the master channel three-states when the SDO port of
the slave channel is active. This allows data to be shifted out of
a slave channel immediately following the completion of data
frame (I/Q pair) shifting out of a master AD6624 channel. To
accomplish this, the SDFE signal of the master channel drives
the SDFS input of the slave channel. Serial output port cascad-
ing can be used with channels on the same AD6624 device, or
with channels on two different devices as shown in Figure 36.
To satisfy t
nel, the SDFE signal from the master channel should be delayed
using a noninverting buffer (e.g., 74LVC244A) that provides a
minimum of 1.5 ns of propagation delay. Figure 36 shows the
cascade capability between two AD6624 devices. The first is
connected as a serial master (SBM = 1) and the second is con-
figured in Serial Cascade mode (SBM = 0).
Using the AD6624 master/slave mode permits a DSP to shift
the data from the master AD6624 serial port, followed immedi-
ately by a frame of data (I and Q words) from the AD6624 slave
port. As shown in Figure 36, the master port is Serial Port 0. The
slave port can be either Serial Port 1, 2, or 3, or a Serial Port 0
from another AD6624. Other AD6624 serial ports can be cascaded
to the slave port by using the SDFE and SDFS in the manner
shown. The only limit to the number of ports that can be cas-
caded comes from serial bandwidth and fan-out considerations.
There must be enough serial clock cycles available to shift the
necessary data into the DSP, and the SCLK (common to all
channels and DSP) must be closely monitored to ensure that it
is a clean signal. For systems where a single DSP serial port will
be connected to many AD6624 serial ports, it is recommended
that the SCLK signal from the master be buffered to the slaves.
See Serial Port Buffering in the Applications section.
Figure 35. Typical Serial Data Output Interface to DSP
(Serial Slave Mode, SBM = 0)
SSF
AD6624
CH 0
SBM0
and t
SDIV0
4
HSF
SCLK
SDFS
SDFE
SDO
SDI
timing requirements of the slave chan-
10k
10k
SCLK
DR
RFS
DT
DSP
–26–
Serial Output Frame Timing (Master and Slave)
The SDFS signal transitions accordingly depending on whether
the part is in Master (SBM = 1, Figure 43) or Slave (SBM = 0,
Figure 32) mode. The next rising edge of SCLK after this occurs
will drive the first bit of the serial data on the SDO pin. The
falling edge of SCLK or the subsequent rising edge can then be
used by the DSP to sample the data until the required number
of bits is received (determined by the serial output port word
length). If the DSP has the ability to count bits, the DSP will
know when the complete frame is received. If not, the DSP can
monitor the SDFE pin to determine that the frame is complete.
Serial Port Timing Specifications
Whether the AD6624 serial channel is operated as a Serial Bus
Master or as a Serial Slave, the serial port timing is identical.
Figures 38 to 44 indicate the required timing for each of the
specifications.
SCLK
CLK
Figure 38. SCLK Switching Characteristics (Divide by 1)
Figure 36. Typical Serial Data Output Interface to DSP
(Serial Cascade Mode, SBM = 0)
SCLK
Figure 37. SCLK Timing Requirements
AD6624
CH 0
MASTER
AD6624
CH 0
CASCADE
SBM0
SDIV0
t
3.3V
DSCLKH
4
SCLK
SDFS
SDFE
SCLK
SDFS
SDFE
SDO
SDO
SDI
SDI
t
SCLKL
t
SCLKL
BUFFER
t
SCLKH
t
SCLK
t
SCLK
DT
DR
RFS
SCLKH
10k
DSP
10k
REV. B