CY7C0853V-100BBI Cypress Semiconductor Corp, CY7C0853V-100BBI Datasheet - Page 12

• Manufacturer Part Number: CY7C0853V-100BBI
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C0853V-100BBI

• Density: 9Mb
• Access Time (max): 4.7ns
• Sync/async: Synchronous
• Architecture: SDR
• Clock Freq (max): 100MHz
• Operating Supply Voltage (typ): 3.3V
• Address Bus: 18b
• Package Type: FBGA
• Operating Temp Range: -40C to 85C
• Number Of Ports: 2
• Supply Current: 310mA
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 172
• Word Size: 36b
• Number Of Words: 256K
• Lead Free Status / RoHS Status: Not Compliant

IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C0850AV/CY7C0851AV/CY7C0852AV/CY7C0853AV
incorporates an IEEE 1149.1 serial boundary scan test access
port (TAP). The TAP controller functions in a manner that does
not conflict with the operation of other devices using
1149.1-compliant
JEDEC-standard 3.3V I/O logic levels. It is composed of three
input connections and one output connection required by the test
logic defined by the standard.
Table 4. Identification Register Definitions
Table 5. Scan Registers Sizes
Table 6. Instruction Identification Codes
Notes
Document #: 38-06070 Rev. *H
Revision Number (31:28)
Cypress Device ID (27:12)
Cypress JEDEC ID (11:1)
ID Register Presence (0)
EXTEST
BYPASS
IDCODE
HIGHZ
CLAMP
SAMPLE/PRELOAD
NBSRST
RESERVED
12. The “X” in this diagram represents the counter upper bits.
13. Boundary scan is IEEE 1149.1-compatible. See “Performing a Pause/Restart” for deviation from strict 1149.1 compliance.
14. See details in the device BSDL files.
Instruction
Instruction Field
TAPs.
Register Name
Boundary Scan
All other codes Other combinations are reserved. Do not use other than the above.
Identification
Instruction
Bypass
Code
The
0000
1000
1011
0111
0100
1100
1111
TAP
C001h
C002h
C092h
Value
034h
0h
1
Captures the Input/Output ring contents. Places the BSR between the TDI and TDO.
Places the BYR between TDI and TDO.
Loads the IDR with the vendor ID code and places the register between TDI and TDO.
Places BYR between TDI and TDO. Forces all CY7C0851AV/CY7C0852AV/
CY7C0853AV output drivers to a High-Z state.
Controls boundary to 1/0. Places BYR between TDI and TDO.
Captures the input/output ring contents. Places BSR between TDI and TDO.
Resets the non-boundary scan logic. Places BYR between TDI and TDO.
operates
Reserved for version number.
Defines Cypress part number for the CY7C0851AV
Defines Cypress part number for the CY7C0852AV and CY7C0853AV
Defines Cypress part number for the CY7C0850AV
Allows unique identification of the DP family device vendor.
Indicates the presence of an ID register.
using
[13]
Performing a TAP Reset
A reset is performed by forcing TMS HIGH (V
edges of TCK. This reset does not affect the operation of the
devices, and may be performed while the devices are operating.
An MRST must be performed on the devices after power up.
Performing a Pause/Restart
When a SHIFT-DR PAUSE-DR SHIFT-DR is performed the scan
chain outputs the next bit in the chain twice. For example, if the
value expected from the chain is 1010101, the device outputs a
11010101. This extra bit causes some testers to report an
erroneous failure for the devices in a scan test. Therefore the
tester should be configured to never enter the PAUSE-DR state.
Description
Description
CY7C0850AV, CY7C0851AV
CY7C0852AV, CY7C0853AV
Bit Size
n
32
[14]
4
1
DD
) for five rising
Page 12 of 32
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