STK14C88-5LF35M Cypress Semiconductor Corp, STK14C88-5LF35M Datasheet - Page 6

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STK14C88-5LF35M

Manufacturer Part Number
STK14C88-5LF35M
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of STK14C88-5LF35M

Lead Free Status / RoHS Status
Compliant
SRAM Read Cycles #1 and #2
(VCC = 5.0V ± 10%)
Document Number: 001-52038 Rev. *B
Notes
6. W and HSB must be high during SRAM read cycles.
7. I/O state assumes E and G
8. Measured ± 200 mV from steady state output voltage.
NO.
10
11
1
2
3
4
5
6
7
8
9
t
AVAV
t
t
ELICCH
EHICCL
t
t
t
t
AXQX
EHQZ
GHQZ
#1, #2
t
t
t
t
[6]
AVQV
DQ (DATA OUT)
GLQV
GLQX
ELQV
ELQX
,
t
ELEH
ADDRESS
[7]
[8]
[8]
7
[5]
[5]
Symbols
[4]
[6]
<
V
IL
t
t
t
Alt.
t
t
t
and W ≥ V
ACS
t
t
OHZ
t
t
t
OLZ
RC
OE
OH
AA
HZ
PA
PS
LZ
Figure 4. SRAM Read Cycle 1: Address Controlled
Figure 5. SRAM Read Cycle 2: E and G Controlled
IH
; device is continuously selected.
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Address Change or Chip Enable to
Output Active
Address Change or Chip Disable to
Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
t
AXQX
5
10
6
Parameter
3
8
4
t
AVQV
3
t
1
AVAV
2
2
STK14C88-25 STK14C88-35 STK14C88-45
Min
25
DATA VALID
5
5
0
0
Max
10
10
25
25
10
25
29
[6, 7]
[6]
Min
35
5
5
0
0
9
Max
35
35
15
13
13
35
7
11
Min
45
5
5
0
0
STK14C88
Max
45
20
15
15
45
45
Page 6 of 19
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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