STK12C68-CF35 Cypress Semiconductor Corp, STK12C68-CF35 Datasheet - Page 9

• Manufacturer Part Number: STK12C68-CF35
• Manufacturer: Cypress Semiconductor Corp

Specifications of STK12C68-CF35

• Lead Free Status / RoHS Status: Compliant

Document Control #ML0008 Rev 2.0
The STK12C68, STK12C68-5 has two separate
modes of operation:
mode. In
standard fast static
is transferred from
(the
to
functions are disabled.
NOISE CONSIDERATIONS
The STK12C68, STK12C68-5 is a high-speed mem-
ory and so must have a high-frequency bypass
capacitor
between V
are as short as possible. As with all high-speed
CMOS
and signals will help prevent noise problems.
SRAM READ
The STK12C68, STK12C68-5 performs a
cycle whenever E and G are low and W and HSB
are high. The address specified on pins A
mines which of the 8,192 data bytes will be
accessed. When the
transition, the outputs will be valid after a delay of
t
G, the outputs will be valid at t
ever is later (
repeatedly respond to address changes within the
t
any control input pins, and will remain valid until
another address change or until E or G is brought
high, or W or HSB is brought low.
SRAM WRITE
A
low and HSB is high. The address inputs must be
stable prior to entering the
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ
before the end of a W controlled
before the end of an E controlled
It is recommended that G be kept high during the
entire
common I/O lines. If G is left low, internal circuitry
will turn off the output buffers t
AVQV
AVQV
WRITE
SRAM
0-7
STORE
(
access time without the need for transitions on
June, 2008
READ
will be written into the memory if it is valid t
WRITE
ICs, normal careful routing of power, ground
(the
cycle is performed whenever E and W are
SRAM
CAP
of
cycle #1). If the
operation) or from Nonvolatile Elements
RECALL
cycle to avoid data bus contention on
READ
and V
approximately
mode, the memory operates as a
RAM
cycle #2). The data outputs will
SRAM
SS
READ
operation). In this mode
SRAM
, using leads and traces that
. In nonvolatile mode, data
is initiated by an address
to Nonvolatile Elements
READ
WRITE
mode and nonvolatile
WLQZ
ELQV
0.1μF
WRITE
is initiated by E or
after W goes low.
or at t
cycle and must
DEVICE OPERATION
WRITE
.
GLQV
connected
0-12
STK12C68, STK12C68-5 (SMD5962-94599)
, which-
or t
SRAM
deter-
READ
DVWH
DVEH
9
be initiated and will take t
is initiated by executing sequential
During the
nonvolatile data is first performed, followed by a pro-
gram of the nonvolatile elements. The program
operation copies the
input and output are disabled until the cycle is com-
pleted.
Because a sequence of
the sequence, or the sequence will be aborted and
no
trolled
Once the sixth address in the sequence has been
entered, the
and not
POWER-UP RECALL
During power up, or after any low-power condition
(V
latched. When V
voltage of V
If the STK12C68, STK12C68-5 is in a
the end of power-up
corrupted. To help avoid this situation, a 10K Ohm
resistor should be connected either between W and
system V
SOFTWARE NONVOLATILE STORE
The STK12C68, STK12C68-5 software
READ
memory. Once a
addresses is used for
that no other
To initiate the software
READ
The software sequence must be clocked with E con-
chip will be disabled. It is important that
although it is not necessary that G be low for the
sequence to be valid. After the t
been fulfilled, the
READ
CAP
1. Read address
2. Read address
3. Read address
4. Read address
5. Read address
6. Read address
STORE
< V
sequence must be performed:
and
READ
cycles from six specific address locations.
CC
WRITE
RESET
or
WRITE
or between E and system V
STORE
SWITCH
s.
RECALL
STORE
READ
), an internal
CAP
cycles be used in the sequence,
, a
operation.
SRAM
STORE
cycle an erase of the previous
or
0000 (hex)
1555 (hex)
0AAA (hex)
1FFF (hex)
10F0 (hex)
0F0F (hex)
once again exceeds the sense
RECALL
RECALL
cycle will commence and the
will take place.
STORE
WRITE
SRAM
STORE
RESTORE
will again be activated for
cycle is initiated, further
RECALL
, the
cycle will automatically
initiation, it is important
READ
accesses intervene in
data into nonvolatile
to complete.
cycle, the following
STORE
Valid READ
Valid READ
Valid READ
Valid READ
Valid READ
Initiate STORE cycle
SRAM
s from specific
request will be
cycle time has
WRITE
CC
STORE
E
READ
data will be
.
controlled
state at
cycles
cycle