STK10C68C55M Cypress Semiconductor Corp, STK10C68C55M Datasheet - Page 4

• Manufacturer Part Number: STK10C68C55M
• Manufacturer: Cypress Semiconductor Corp
• Type: NVSRAMr

Specifications of STK10C68C55M

• Word Size: 8b
• Organization: 8Kx8
• Density: 64Kb
• Interface Type: Parallel
• Access Time (max): 55ns
• Operating Supply Voltage (typ): 5V
• Package Type: CDIP
• Operating Temperature Classification: Military
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• Operating Temp Range: -55C to 125C
• Pin Count: 28
• Mounting: Through Hole
• Supply Current: 55mA
• Lead Free Status / RoHS Status: Compliant

March 2006
STK10C68
SRAM WRITE CYCLES #1 & #2
Note i:
Note j:
SRAM WRITE CYCLE #1: W Controlled
SRAM WRITE CYCLE #2: E Controlled
NO.
12
13
14
15
16
17
18
19
20
21
ADDRESS
DATA OUT
ADDRESS
DATA OUT
DATA IN
t
DATA IN
WLQZ
t
t
t
t
t
t
t
t
t
WLWH
DVWH
WHDX
WHAX
WHQX
ELWH
AVWH
AVWL
If W is low when E goes low, the outputs remain in the high-impedance state.
E or W must be ≥ V
AVAV
#1
W
E
h, i
W
E
SYMBOLS
t
t
t
t
t
t
t
t
WLEH
DVEH
EHDX
EHAX
ELEH
AVEH
AVEL
AVAV
#2
IH
t
AVWL
t
AVEL
18
during address transitions. NE ≥ V
18
t
t
t
t
t
t
t
Alt.
t
t
t
WC
WP
CW
DW
WR
OW
DH
AW
WZ
AS
PREVIOUS DATA
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
PARAMETER
t
WLQZ
t
20
AVEH
17
t
AVWH
17
t
WLWH
13
IH
t
ELWH
j
.
14
j
t
t
AVAV
AVAV
12
12
HIGH IMPEDANCE
t
4
ELEH
14
t
WLEH
STK10C68-25
13
MIN
25
20
20
10
20
0
0
0
5
HIGH IMPEDANCE
t
DVWH
15
Document Control # ML0006 rev 0.2
MAX
10
t
DVEH
15
DATA VALID
DATA VALID
STK10C68-35
MIN
35
25
25
12
25
0
0
0
5
MAX
13
t
WHDX
STK10C68-45
t
MIN
WHAX
16
45
30
30
15
30
19
0
0
0
5
t
EHDX
t
EHAX
16
19
(V
t
WHQX
MAX
21
14
CC
= 5.0V
STK10C68-55
MIN
55
45
45
30
45
0
0
0
5
MAX
15
±
10%)
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns