STK10C68C55M Cypress Semiconductor Corp, STK10C68C55M Datasheet - Page 3

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STK10C68C55M

Manufacturer Part Number
STK10C68C55M
Description
Manufacturer
Cypress Semiconductor Corp
Type
NVSRAMr
Datasheet

Specifications of STK10C68C55M

Word Size
8b
Organization
8Kx8
Density
64Kb
Interface Type
Parallel
Access Time (max)
55ns
Operating Supply Voltage (typ)
5V
Package Type
CDIP
Operating Temperature Classification
Military
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
4.5V
Operating Temp Range
-55C to 125C
Pin Count
28
Mounting
Through Hole
Supply Current
55mA
Lead Free Status / RoHS Status
Compliant
March 2006
SRAM READ CYCLES #1 & #2
Note f:
Note g: I/O state assumes E, G < V
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlled
SRAM READ CYCLE #2: E Controlled
DQ (DATA OUT)
NO.
DQ (DATA OUT)
10
11
1
2
3
4
5
6
7
8
9
ADDRESS
ADDRESS
W must be high during SRAM READ cycles and low during SRAM WRITE cycles. NE must be high during entire cycle.
t
t
t
t
t
t
t
t
t
t
t
ELQV
AVAV
AVQV
GLQV
AXQX
ELQX
EHQZ
GLQX
GHQZ
ELICCH
EHICCL
#1, #2
I
CC
G
f
E
g
g
h
h
SYMBOLS
e
d, e
t
t
t
t
t
t
t
t
t
t
t
ACS
RC
AA
OE
OH
LZ
HZ
OLZ
OHZ
PA
PS
Alt.
IL
, W > V
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
STANDBY
IH
t
ELICCH
, and NE ≥ V
t
t
ELQX
AXQX
PARAMETER
10
5
t
6
GLQX
8
t
GLQV
IH
4
; device is continuously selected.
f
t
AVAV
t
t
ELQV
2
AVQV
ACTIVE
3
t
1
AVAV
3
2
f, g
STK10C68-25
MIN
25
5
5
0
0
Document Control # ML0006 rev 0.2
MAX
25
25
10
10
10
25
DATA VALID
STK10C68-35
MIN
35
5
5
0
0
MAX
35
35
15
10
10
35
DATA VALID
STK10C68-45
MIN
45
5
5
0
0
(V
t
GHQZ
MAX
CC
9
45
45
20
12
12
45
t
EHQZ
7
t
EHICCL
= 5.0V
STK10C68-55
11
MIN
55
STK10C68
5
5
0
0
MAX
55
55
25
12
12
55
±
10%)
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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