MT18JSF25672PDY-1G1D1 Micron Technology Inc, MT18JSF25672PDY-1G1D1 Datasheet - Page 7

• Manufacturer Part Number: MT18JSF25672PDY-1G1D1
• Manufacturer: Micron Technology Inc

Specifications of MT18JSF25672PDY-1G1D1

• Main Category: DRAM Module
• Sub-category: DDR3 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 256Mx72
• Total Density: 2GByte
• Chip Density: 1Gb
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Operating Current: 1.53A
• Number Of Elements: 18
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

General Description
Fly-By Topology
Registering Clock Driver Operation
Parity Operations
PDF: 09005aef8304aded/Source: 09005aef8304ae2b
JSF18C256x72PD.fm - Rev. A 4/08 EN
The MT18JSF25672PD and MT18JSZF25672PD DDR3 SDRAM modules are high-speed,
CMOS dynamic random access 2GB memory modules organized x72 configurations.
These DDR3 SDRAM modules use internally configured, 8-bank 1Gb DDR3 SDRAM
devices.
DDR3 SDRAM modules use double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially an 8n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for the DDR3 SDRAM module effectively consists of a single
8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
The differential data strobe (DQS, DQS#) is transmitted externally, along with data, for
use in data capture at the DDR3 SDRAM input receiver. DQS is center-aligned with data
for WRITEs. The read data is transmitted by the DDR3 SDRAM and edge-aligned to the
data strobes.
DDR3 SDRAM modules operate from a differential clock (CK and CK#); the crossing of
CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Control, command, and address signals are registered at every positive edge of CK. Input
data is registered on both edges of DQS, and output data is referenced to both edges of
DQS, as well as to both edges of CK.
These DDR3 modules use faster clock speeds than earlier DDR technologies, making
signal quality more important than ever. For improved signal quality, the clock, control,
command, and address buses have been routed in a fly-by topology, where each clock,
control, command, and address pin on each DRAM is connected to a single trace and
terminated (rather than a tree structure, where the termination is off the module near
the connector). Inherent to fly-by topology, the timing skew between the clock and DQS
signals can be easily accounted for by using the write leveling feature of DDR3.
Registered DDR3 SDRAM modules use a registering clock driver consisting of a register
and a phase-lock loop (PLL) and comply with JEDEC standard “Definition of the
SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3
RDIMM Applications.”
The register section of the registering clock driver latches command and address input
signals on the rising clock edge. The PLL section of the registering clock driver receives
and redrives the differential clock signals (CK, CK#) to the DDR3 SDRAM devices. The
register(s) and PLL reduce clock, control, command, and address signals loading by
isolating DRAM from the system controller.
The registering clock driver can accept a parity bit from the system’s memory controller,
providing even parity for the control, command, and address bus. Parity errors are
flagged on the E
issue if P
AR
_
IN
and E
RR
_
OUT
RR
_
# pin. Systems not using parity are expected to function without
OUT
2GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
# are left as no connects to the system.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
General Description
©2008 Micron Technology, Inc. All rights reserved