MT9HTF12872PY-800E1 Micron Technology Inc, MT9HTF12872PY-800E1 Datasheet - Page 12
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MT9HTF12872PY-800E1
Manufacturer Part Number
MT9HTF12872PY-800E1
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT9HTF12872PY-800E1.pdf
(23 pages)
Specifications of MT9HTF12872PY-800E1
Main Category
DRAM Module
Sub-category
DDR2 SDRAM
Module Type
240RDIMM
Device Core Size
72b
Organization
128Mx72
Total Density
1GByte
Chip Density
1Gb
Maximum Clock Rate
800MHz
Operating Supply Voltage (typ)
1.8V
Operating Current
1.71A
Number Of Elements
9
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Pin Count
240
Mounting
Socket
Lead Free Status / RoHS Status
Compliant
I
Table 10: DDR2 I
Values shown for MT47H32M8 DDR2 SDRAM only and are computed from values specified in the 256Mb (32 Meg x 8)
component data sheet
PDF: 09005aef82250868
htf9c32_64_128x72.pdf - Rev. F 3/10 EN
Parameter
Operating one bank active-precharge current:
(I
mands; Address bus inputs are switching; Data bus inputs are switching
Operating one bank active-read-precharge current: I
CL = CL (I
t
bus inputs are switching; Data pattern is same as I
Precharge power-down current: All device banks idle;
is LOW; Other control and address bus inputs are stable; Data bus inputs are
floating
Precharge quiet standby current: All device banks idle;
CKE is HIGH, S# is HIGH; Other control and address bus inputs are stable; Data
bus inputs are floating
Precharge standby current: All device banks idle;
HIGH, S# is HIGH; Other control and address bus inputs are switching; Data
bus inputs are switching
Active power-down current: All device banks open;
t
are stable; Data bus inputs are floating
Active standby current: All device banks open;
MAX (I
Other control and address bus inputs are switching; Data bus inputs are switch-
ing
Operating burst write current: All device banks open; Continuous burst
writes; BL = 4, CL = CL (I
=
inputs are switching; Data bus inputs are switching
Operating burst read current: All device banks open; Continuous burst
read, I
MAX (I
Address bus inputs are switching; Data bus inputs are switching
Burst refresh current:
interval; CKE is HIGH, S# is HIGH between valid commands; Other control and
address bus inputs are switching; Data bus inputs are switching
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and ad-
dress bus inputs are floating; Data bus inputs are floating
DD
RCD =
CK (I
DD
t
RP (I
),
DD
Specifications
t
RAS =
OUT
DD
DD
DD
t
); CKE is LOW; Other control and address bus inputs
RCD (I
DD
),
),
); CKE is HIGH, S# is HIGH between valid commands; Address bus
= 0mA; BL = 4, CL = CL (I
t
t
), AL = 0;
RP =
RP =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
t
t
RP (I
RP (I
DD
t
CK =
DD
DD
Specifications and Conditions – 256MB
DD
DD
t
); CKE is HIGH, S# is HIGH between valid commands;
); CKE is HIGH, S# is HIGH between valid commands;
CK =
), AL = 0;
); CKE is HIGH, S# is HIGH between valid com-
t
CK (I
t
256MB, 512MB, 1GB (x72, ECC, SR) 240-Pin DDR2 SDRAM RDIMM
CK (I
DD
),
DD
DD
t
CK =
t
), AL = 0;
RC =
); REFRESH command at every
t
CK (I
t
RC (I
t
DD
CK =
DD
),
),
t
DD4W
CK =
t
t
t
RAS =
CK =
t
RAS =
t
CK (I
CK =
t
CK =
t
CK (I
t
DD
CK (I
t
OUT
t
CK =
t
t
RAS MAX (I
t
CK (I
RAS MIN (I
CK =
),
12
DD
t
= 0mA; BL = 4,
DD
RAS =
Fast PDN exit
MR[12] = 0
Slow PDN exit
MR[12] = 1
),
t
DD
CK (I
),
t
t
CK (I
); CKE is
RAS =
t
RC =
t
RFC (I
t
DD
RAS
DD
DD
DD
Micron Technology, Inc. reserves the right to change products or specifications without notice.
); CKE
t
),
t
),
);
RC
RAS
DD
t
RP
)
Symbol
I
I
I
I
I
I
I
DD4W
I
I
DD2Q
I
I
DD2N
DD3N
DD4R
DD2P
DD3P
DD0
DD1
DD5
DD6
-667
1710
1620
1620
810
900
360
360
270
450
45
54
45
© 2003 Micron Technology, Inc. All rights reserved.
I
DD
1440
1350
1530
-53E
720
810
315
315
225
360
45
54
45
Specifications
1125
1035
1485
-40E
675
765
225
270
180
270
45
54
45
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA