KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 40

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

Functional Description
Figure 4-8. MSIO Register Read Transaction
Figure 4-9. MSIO Register Write Transaction
4.11.4
4-12
CMD
SCK
SIO
CMD
SCK
SIO
T
Note: The DMH samples data on clock edges indicated by arrows.
Note: The DMH samples data on clock edges indicated by arrows.
11 11 00 00
0
T
1111 0000
0
T
4
T
4
SIO is driven by the DMH for the SD packet of an MSIO Register Read transaction (see
Figure
MSIO Register Write transaction (see
DMH ignores the contents of the SINT packets, and does not drive the bus during this interval.
When an MSIO Register Read transaction is performed, a turnaround clock is placed in front of
(T52), and after (T69), the SD packet (see
these two clocks.
The DMH also detects a certain sequence on CMD as a serial I/O reset. Refer to
“MSIO Local Reset”
The DMH integrates an I
maximum of eight SPD EEPROMs associated with each I
as indicated in
BSIO Bus Interface
SWR
4-8). SIO is driven by the SNC to provide the SRD and SA packets. Additionally, for an
SRD
Figure
T
T
20
20
for details.
4-10.
2
C controller to access the DIMM SPD EEPROMs. There can be a
SA
SA
Figure
T
T
36
Figure
36
4-9), the SD packet is also driven by the SNC. The
Intel
4-10). The SNC must not drive the bus during
®
E8870DH DDR Memory Hub (DMH) Datasheet
SD
SINT
2
C bus; thus, the I
T
0
T
52
52
SINT
2
SD
C interfaces are wired
Section 4.13.4,
T
T
0
68
1 111 0 000
70
11110000
001187
001188