KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet
KC82870DH S L5X2
Specifications of KC82870DH S L5X2
Related parts for KC82870DH S L5X2
KC82870DH S L5X2 Summary of contents
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... Intel 82870DH DDR Memory Hub (DMH) Datasheet Product Features Two independent DDR DIMM channels per DMH. — 4 DIMMs per DDR Channel. — Registered PC1600 DDR DIMMs. Write Buffers to minimize large turnaround times. Pass through architecture for Read and Write accesses. ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling1-800-548- 4725 visiting Intel's website at http://www.intel.com. ...
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... MCP for DIMM Read/Write Command ..................................................4-4 4.2.5 MCP for Extended Commands..............................................................4-4 4.3 DMH Time Synchronization Packet....................................................................4-4 4.4 Main Channel Periodic Calibration .....................................................................4-5 4.4.1 Current Calibration ................................................................................4-5 4.4.2 Temperature Calibration........................................................................4-5 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet iii ...
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... DDR Interface ....................................................................................................5-3 5.4.1 Signal Group .........................................................................................5-3 5.4.2 DDR Reference Voltage Requirements ................................................5-4 5.4.3 DC Specifications.................................................................................. 5-4 5.4.4 AC Specifications .................................................................................. 5-4 5.5 Miscellaneous Signals Interface.........................................................................5-6 5.5.1 Signal Groups .......................................................................................5-6 5.5.2 DC Characteristics ................................................................................5-6 5.5.3 AC Specification ....................................................................................5-7 iv ® Intel E8870DH DDR Memory Hub (DMH) Datasheet ...
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... DMH Main Channel Signal Groups ....................................................................5-2 5-4 Main Channel Vref Specification ........................................................................5-2 5-5 RSL Data Group, DC Parameters ......................................................................5-2 5-7 Main Channel “CMOS 1.8 I/O” DC Parameters .................................................5-3 5-6 RSL Clocks, DC Parameters..............................................................................5-3 5-8 DMH DDR Signal Groups...................................................................................5-3 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet v ...
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... CMOS 2.5V AC Parameters ..............................................................................5-8 5-19 CMOS 1.8V Output AC Parameters ..................................................................5-8 6-1 DMH Ball List .....................................................................................................6-4 6-2 DMH Signal – Ball Number ..............................................................................6-12 7-1 Parametric Test Control Signals ........................................................................ 7-1 7-2 Parametric Test Pin Order .................................................................................7-1 vi ® Intel E8870DH DDR Memory Hub (DMH) Datasheet ...
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... The DMH interfaces two 8-byte-wide DDR DIMM channels to a single, 2-byte-wide Main Channel as shown in DMH supports a maximum of 8 DIMMs (4 each on each branch channel), and requires at least 1 DIMM. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet DMH Branch Channel 0 Main Channel Branch Channel 1 ...
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... Registered DDR DIMM Each Branch Channel 72 Bits Supports 200 MT/s Branch DMH Channel 0 Channel 1 Main Channel 18 Bits Supports 800 MT/s 1 PC1600 DDR SDRAM memory ® Intel E8870DH DDR Memory Hub (DMH) Datasheet 72 Bits Branch CMD1 CS1[7:0] Main Channel (Rambus* Signals) 001177a ...
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... Bank x 9 DRAMs/Side x 2 Sides 64M x 4 bit x 4 Bank x 18 DRAMs/Side x 1 Side Scalable Node Controller. Processor system bus interface and memory controller for the Intel RAMBUS Signaling Level. The name of the signaling technology used by RAMBUS. ...
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... The Main Channel Serial I/O bus. Uses the RAC serial I/O CMOS signals. The Branch Channel Serial I/O bus. This is the DIMM Serial Presence Detect interface. Mega-Transfers per second. Description ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Date August 2002 ...
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... Table 2-1. Main Channel Interface Signals Signal DQA[8:0] DQB[8:0] RQ[7:0] SIO SCK CMD CTM CTMN ® Intel E8870DH DDR Memory Hub (DMH) Datasheet State during Type PWRGOOD Deassertion I/O ? Data Bus, Data Byte A: RSL Bidirectional 9-bit data bus A. These correspond to the DQA[8:0] signals on the RAC ...
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... CS#[7] which selects the last row SDRAM Clock Enable: SSTL_2 These signals are used for signaling commands to an Class II SDRAM row. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Description 2-2, signals on BC0 and BC1 are Description ...
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... SCL 2.3 Reset and Test Signals Table 2-3. Reset and Miscellaneous Signals Signal TSO PWRGOOD RESET# XORIN XOROUT ® Intel E8870DH DDR Memory Hub (DMH) Datasheet State during Type PWRGOOD Deassertion O L SDRAM Clocks: SSTL_2 H One pair of differential clock signals for each DIMM. ...
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... CMD, SCK, and SIO pins. Filtered Analog V : Provide V to RAC interface DLL Filtered 1.8V for the DMH internal delay cells. 2.5V source for DDR and 2.5V I/Os. Ground DDR Address VREF DDR VREF DDR VREF Vss ® Intel E8870DH DDR Memory Hub (DMH) Datasheet ...
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... Branch Channel 1, DIMM 7 Strobe Offset (t Bits [15:14 13:12 Branch Channel 1, DIMM 6 Strobe Offset (t Bits [13:12 11:10 Branch Channel 1, DIMM 5 Strobe Offset (t Bits [11:10 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Interface”). Description Description ): DSD7 in CFMs DSD7 DSD6 in CFMs DSD6 ...
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... Branch Channel 0, DIMM 1 Strobe Offset (t Bits [3: 1:0 Branch Channel 0, DIMM 0 Strobe Offset (t Bits [1: 3-2 Description ): DSD4 t in CFMs DSD4 DSD3 t in CFMs DSD3 DSD2 t in CFMs DSD2 DSD1 t in CFMs DSD1 DSD0 t in CFMs DSD0 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet ...
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... Main Channel Write Delay (t Specifies additional pipestage delays from the completion of a MCP Write Command, to the beginning of the write data transfer. Bit[4: ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Description ): LVL t in CFMs LVL CWD t in CFMs Bit[4: CFMs ...
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... This bit specifies the number of SCLKs from when a read command is sampled by the SDRAMs to when the DMH samples read data from the SDRAMs. Bit[2: 3-4 Description ): DPL t in CFMs DPL SCLKs CL Reserved Reserved 2 Reserved Reserved 1.5 2.5 Reserved ® Intel E8870DH DDR Memory Hub (DMH) Datasheet ...
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... Access: R/W Size: 16 bits Bit 15 Reserved 14:0 Mode Register Function (MRF): A[14:0] bit values to be used with MRS command of SDI register below. See MRF bits of the SDI register below. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Description Description Registers 3-5 ...
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... Mode Register Set: When DMH receives this command it issues a Mode Register Set (MRS) command. The MRF bits of this register, combine with the preceding MRF register to define the DDR SDRAM Mode register bits. Refer to Jedec Standard JESD79 for Mode Register Set command details. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet ...
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... When set to 1, the execution of the RIC command specified by bits[2:0] starts. After the execution is completed the DMH clears this bit to 0. The software must check to see if this bit is zero before writing to this bit. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Description Reserved Auto Refresh: When the DMH receives this command it issues an Auto Refresh command to the DIMM side specified by the BC and CS bits of this register ...
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... RAC Temperature Calibration: When DMH receives this command it issues a Temperature Calibration sequence to the RAC. Reserved Reserved Reserved Reserved Description Section 4.11.4.3, “BSIO Request Packet for SPD ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Section 4.11.4, “BSIO Section 4.11.4.2, “Clock Divider.” ...
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... RAC Latch Skip Mode (RLSM Skip Mode Enabled Skip Mode Disabled. 3 RAC Skip Mode (RSM Normal mode Use RFSV. 2 RAC Forced Skip Value (RFSV Falling edge of internal RAC clock Rising edge of internal RAC clock. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Description Registers 3-9 ...
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... Default: 8086h Access: R-O Size: 16 bits Identifies the manufacturer of the DMH to be Intel Corporation. Bit 15:0 This is a Vendor Identification Number (VIN) and is assigned by Intel as a 16-bit number (8086h). 3.13 RID – Revision Identification Register Address: 12h Default: 0000h Access: R-O ...
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... R/W BC1: 26H BC0: 7H R/W BC1: 27H BC0: 8H R/W BC1: 28H ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Description Table 3-1 “Unified Access Register Definitions.” Interface”). Table MUARD Bit[5] - Reserved. Bit[4] - Latch Delay Value Bits[3:0] - Iterations per short ...
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... Bit[14] - First-Flag Bit[13] - Last-Flag Bit[12:8] - Start/End Position Bit[7:4] - Second Pattern Bit[3:0] - First Pattern ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Description Clock driver calibration LUT entry 3. Clock driver calibration LUT entry 4. DQ/DQS driver calibration LUT entry 0. DQ/DQS driver calibration LUT entry 1. ...
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... Default: 8765h Access: R-O Size: 16 bits This field distinguishes the device as the DMH. Bit 15:0 The type of Memory Interface - DMH. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Description Section 4.11.4.5, “Changing the Default SPD Description Registers 3-13 ...
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... Registers 3-14 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet ...
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... C specification for a single-master with multiple-slave devices. Figure 4 block diagram of internal logic blocks in the DMH. Refer to Description” for pin descriptions. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Translation”) and sent across the Main Channel interface that is intended for sizing DIMMs. This interface is controlled 4 Chapter 2, “ ...
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... Clock Crossing Logic MSIO Conf iguration Bus Registers DMH Rules”). Managing of the open pages is done by the SNC and the DMH does ® Intel E8870DH DDR Memory Hub (DMH) Datasheet SCLK, SCLK# A,BA RAS,CAS,WE CS,CKE DQ DQS SCLK, SCLK# A,BA RAS,CAS,WE ...
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... MCP for DIMM Activate Command A DIMM Activate Command MCP is translated into a DDR DIMM Activate packet, as defined in Jedec Standard JESD79. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Figure 4-2. The MCP may begin in state state Section 4.3, “DMH Time Synchronization Packet” ...
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... A B State Packet State Packet 0 State State ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Before SNC Sends Commands Before DMH Misinterprets State Packet SNC Sends Sy nc Packet DMH Adjusts Packet After SNC Sends Commands After DMH Correctly Interprets State Packet ...
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... Main Channel, the DMH initiates the RAC temperature calibration process as well as the Branch Channel slew rate calibration (see ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Register”). The Main Channel and Branch Channels must remain quiescent Initialization”). The RIR register (see Section 4.2.5, “ ...
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... Main Channel, the DMH initiates the current calibrate process of Register”). The Main Channel burst length is set by Register”). DIMM burst length and Main Channel burst length ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Section 4.14.4, “DDR Section 4.2.5, “MCP for ...
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... Multiple pages may be open for reading at the same time Activate for Read cannot be issued to a page that is currently opened due to an Activate for Write. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Functional Description Register”) such that it has the same ...
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... Writes must always be of natural alignment. 2. Read alignments shown in 3. The DMH Write buffer provides the burst operation support on a read-hit as defined in Table 4-2. 4 ACT Table 4-2 are the only alignments supported. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Wr 3 ACT 001182a ...
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... SCLK (SDRAM clocks) for the DDR DIMMs. There MHz serial I/O clock input for the MSIO bus, which is used to generate a 100 kHz serial I/O clock on the DDR DIMM side. The 1 MHz MSIO clock must be provided at all times. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Starting Address Sequential Mode ...
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... Figure 4-6. Register Read MSIO Transaction SCK SRQ SA SINT SD 4-10 CFM SNC RAC CTM RAC Figure 4-6 and Reserved SOP[3:0] Reserved SA[11:0] 0 SD[15:0] ® Intel E8870DH DDR Memory Hub (DMH) Datasheet V term DRCG DMH 001183a Figure 4-7 show the layout of Register Reserved C[2:0] 001185 ...
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... The MSIO bus is a three-pin low-speed CMOS serial interface. SCK and CMD are input-only, and SIO is bi-directional. SCK is driven by the SNC MHz. CMD is driven by the SNC, and is used to indicate the beginning of a new command reset sequence. CMD is sampled on both edges of SCK by the DMH. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet ...
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... SD packet is also driven by the SNC. The Figure 4-10). The SNC must not drive the bus during for details SINT controller to access the DIMM SPD EEPROMs. There can be a 4-10. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Section 4.13. 11110000 001187 111 0 000 SINT 001188 ...
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... EEPROM does not acknowledge a packet at any of the required ACK points. The second condition occurs when an EEPROM throttles the serial clock for more than 25 ms. These conditions generate the same end result (BBE field set to 1). ® Intel E8870DH DDR Memory Hub (DMH) Datasheet SA0 DIMM ...
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... Byte Address. The Write Data is passed in the SD[7:0] ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Table 4-4 provides the available SCL 2 C Slave Address, while SA[7:0] field Section 3.10, “SPD – Serial Presence DATA Slave Address, while the SA[7: 001190 ...
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... Section 3.7, “SDI – SDRAM Initialization used by BIOS to cause specific initialization sequences to be sent to the DIMMs over the DIMM command lines. Table 4-5 commands available through the SDI register. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Register”). Byte Address A R ...
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... RAS# CAS 4-13) is used when SCK begins before PWRGOOD assertion. In this CC T0 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet WE# Address Opcode Bank Address - Table 2-1, Table 2-2, and Table 2-3, Section 4.14, “Initialization.” T1 Ready f or Serial Commands and 001192 ...
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... CMD resets the state machines controlling the MSIO pins. Programmable registers in the DMH are not affected by this reset. Figure 4-15. SIO Reset Sequence 0 SCK CMD ® Intel E8870DH DDR Memory Hub (DMH) Datasheet (Figure 4-14) is used when SCK begins after PWRGOOD assertion. In this ...
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... Section 3.7, “SDI – SDRAM Initialization Register”) to match the DIMM CAS latency. Program the DTS field (Section 3.3, “MCTIM – Main Channel Timing ® Intel E8870DH DDR Memory Hub (DMH) Datasheet has occurred, the DMH Section 4.11.2, “MSIO Section 4.11.4, “BSIO Bus Interface” ...
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... For each DIMM side, BIOS must determine and program the t Channel Timing Register”) and t register values. The DMH provides an assist circuit to assist BIOS in ascertaining these values. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet (Section 3.4, “BCTIM – Branch DPL (Section 3.2, “DSTIM – DIMM Strobe Timing ...
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... Functional Description 4-20 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet ...
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... VCC25 DDR I/O Interface VCC25-Icc DDR I/O Interface Supply Current VCC25- DDR I/O Interface Transient Current dIccA/dt Slew Rate ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Parameter Min –10 –0.50 –0.50 are specified at the pin of the package. Parameter Min 1 ...
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... CFM, CFMN (differential clock); CTM, CTMN (differential clock) a SCK, CMD, PWRGOOD SIO b VCCRAC, VCCRACA , VREF{A,B} RAC Parameter Min 1. Parameter Min Vref, r –0.5 Vref, r +0.175 0.54 –15% REF ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Signal c , VSS Typ Max Units Notes a 1.40 1.53 V Max Unit Notes c Vref, r –0.175 V c Vref ...
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... Ilo Output Leakage Current a. All specifications are at the pin of the package. b. Parameters apply to “CMOS 1.8” input, output, and I/O buffers. c. VCCRIO is the VCC I/O as specified in Intel 5.3.3 AC Specifications For complete RAMBUS data sheet, including the AC specifications, timing relationships, etc., please refer to the RAMBUS website. ...
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... Vref –0. Parameter Min –0.30 Vref, d +0.10 Vtt +0.52 –15.4 Parameter Min 1.7 6.7 4.4 9.6 –75 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Typ Max Units Notes a, b (VCC25)/2 V (VCC25)/2 +0.025 a, c Vref Vref +0.04 V Max Unit Notes Vref, d – ...
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... AC Waveforms Figure 5-1. SSTL-2 Common Clock AC Timing Clock from DMH Tdqsck min DQS at DMH Clock from DMH Tacck min A/C at DMH ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Parameter Min 1.50 1.50 –1.65 3.14 0.50 1.80 0. Parameter Min 0.45 ...
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... Tvb = Valid Data before the Strobe Tva = Valid Data after the Strobe Tds = Data Setup to Strobe Tdh = Data Hold to Strobe Input RESET#, PWRGOOD, XORIN XOROUT b SDA, SCL, TSO a Parameter ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Tdh VREF Valid Data Tds Signal Min Max Unit 1 ...
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... SCK (neg) -to-SIO Delay Thr SCK (pos) -to-SIO Delay a. Specified by design characterization. b. Overshoot/undershoot duration less than 5 ns. c. @CLOAD, max = 20pf (SD read data valid). d. @CLOAD, max = 20pf (SD read data hold). ® Intel E8870DH DDR Memory Hub (DMH) Datasheet a Parameter Min – Parameter Min 1 ...
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... Supply voltage at 1.5V ±5% tolerance. c. Clock delay is in reference to the 200 MHz clock. 5-8 a Parameter Min 0.5 N/A N Parameter Min 4.7 4.0 250 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Max Unit Notes 2 V/ns 3 V/ns Max Unit Notes 100 kHz ...
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... A heatsink, with appropriate interface material and retention capabilities, is required for proper operation. Figure 6-1. 567-Ball (DMH) OLGA1 Package Dimensions – Top View Handling Exclusion Area 0.546 in. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Table 6-1 0.666 in. 0.366 in. 0.100 in. ...
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... Ballout and Package Information Figure 6-2. 567-Ball (DMH) OLGA1 Package Dimensions – Bottom View 4X 0.635 4X 15.500 23X 1.270 NOTE: All dimensions are in millimeters. 6 1112 21222324 23X 1.270 8X 14.605 31.000 ±0.100 0.200 A -B- ® Intel E8870DH DDR Memory Hub (DMH) Datasheet 31.000 ±0.100 -A- 001235 ...
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... Figure 6-3. 567-Ball (DMH) OLGA1 Solder Balls Detail OLGA Substrate Die J 1.940 ±0.150 NOTE: All dimensions are in millimeters. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Ballout and Package Information H 0.74 ±0.025 Underfill Epoxy 1.100 ±0.100 0.600 ±0.100 BGA Solder Balls Detail H 0.100 ± ...
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... C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Signal BC1CS#[0] VSS BC1SCLK[2] BC1SCLK#[2] VSS BC1DQ[16] BC1DQ[20] VCC25 BC0DQ[17] BC0DQ[21] VCC25 BC0SCLK#[3] BC0SCLK[3] VCC25 BC0CS#[1] BC0A[0] VCC25 BC0A[7] BC0A[9] ...
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... VCC25 E14 BC1A[11] E15 BC1A[5] E16 VCC25 E17 BC1CS#[6] E18 BC1CS#[5] E19 VCC25 E20 BC1DQ[9] E21 BC1DQ[13] E22 VCC25 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Ballout and Package Information Signal Ball Number E23 E24 F10 F11 F12 F13 F14 ...
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... J23 J24 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Signal BC0DQ[3] BC0DQ[2] VCC25 N/C N/C VSS VCCRAC VSS VCCRAC VSS AD1VREF a TSO 330-ohm P/D VCC25 BC1DQ[2] BC1DQ[3] VCC25 BC1DQ[11] BC1DQ[28] ...
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... L24 BC1DQS[12] M2 BC0DQ[27] M3 BC0DQ[31] M4 VSS M5 BC0DQ[65] M6 BC0DQ[64] M7 VSS M8 BC0VSSAB M9 VCCDLY M10 VCC25 M11 VSS ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Ballout and Package Information Signal Ball Number M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 ...
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... T15 T16 T17 T18 T19 T20 T21 T22 T23 T24 U10 U11 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Signal VCC25 BC1DQ[34] BC1DQS[13] VCC25 BC0DQ[38] VSS BC0DQ[39] BC0DQ[35] VSS BC0DQ[60] BC0DQ[61] VSS BC0VREFC VCC25 VSS VCCRAC VSS VCCRAC VSS BC1VREFC ...
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... BC1DQ[58] V18 VSS V19 BC1DQS[16] V20 BC1DQ[49] V21 VSS V22 BC1DQ[53] V23 BC1DQ[45] V24 VSS W1 BC0DQ[41] W2 VCC25 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Ballout and Package Information Signal Ball Number W10 W11 W12 W13 W14 W15 W16 W17 W18 ...
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... AC8 AC9 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Signal RQ[1] VSS RQ[4] VSS VREFARAC VSS CFMN VSS DQA[2] VSS DQA[5] VSS BC1DQ[51] VSS BC1DQ[46] ...
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... AD24 BC1DQ[47] a. TSO strapped to GND for normal operation. When TSO is driven high, it will enter Parametric Test Mode. Refer to Section 7.1, “Parametric Test Mode” ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Ballout and Package Information Signal for more information. 6-11 ...
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... BC0DQ[34] F12 BC0DQ[35] B7 BC0DQ[36] C8 BC0DQ[37] D6 BC0DQ[38] D7 BC0DQ[39] D9 BC0DQ[4] E7 BC0DQ[40] E8 BC0DQ[41] F8 BC0DQ[42] H8 BC0DQ[43] K7 BC0DQ[44] H4 BC0DQ[45] J3 BC0DQ[46] D3 BC0DQ[47] E4 BC0DQ[48] G4 BC0DQ[49] G3 BC0DQ[5] B2 BC0DQ[50] AB3 BC0DQS[6] U4 BC0DQS[7] V3 BC0DQS[8] W4 BC0DQS[9] ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Ball Number AA2 AC2 U2 V2 AB1 AD1 AA3 ...
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... BC0DQS[11] BC0DQS[12] BC0DQS[13] BC0DQS[14] BC0DQS[15] BC0DQS[16] BC0DQS[17] BC0DQS[2] BC0DQS[3] BC0DQS[4] BC0DQS[5] BC1CKE BC1CS#[0] BC1CS#[1] BC1CS#[2] BC1CS#[3] BC1CS#[4] BC1CS#[5] ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Ballout and Package Information Ball Number Signal Y4 BC0RAS# W7 BC0SCLK[0] Y6 BC0SCLK[1] V8 BC0SCLK[2] R8 BC0SCLK[3] K6 BC0SCLK#[0] T6 BC0SCLK#[1] ...
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... E20 CFMN H20 CMD F20 CTM F22 CTMN E23 DQA[0] L24 DQA[1] R23 DQA[2] Y24 DQA[3] ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Ball Number AA23 AC23 U23 V23 AB24 AD24 U20 V20 G19 AA22 AB22 U21 V22 W21 Y21 ...
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... P/D RQ[4] RQ[5] RQ[6] RQ[7] SREFFB SREF SCK SCL SDA 330-ohm P/D N/C SIO N/C ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Ballout and Package Information Ball Number Signal W22 DQA[4] V19 DQA[5] N19 DQA[6] D24 DQA[7] K21 DQA[8] ...
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... VREFARAC P10 VREFBRAC R1 VSS R4 VSS R7 VSS R15 VSS R18 VSS R21 VSS R24 VSS T10 VSS U3 VSS U6 VSS ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Ball Number E6 E9 E12 E13 E16 E19 E22 G17 G20 G23 J18 J21 J24 K10 L3 ...
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... VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Ballout and Package Information Ball Number Signal U11 VSS U14 VSS U19 VSS U22 VSS W2 VSS W5 VSS ...
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... VSS T17 VSS T20 VSS T23 VSS V1 XORIN V4 XOROUT V7 XORIN V15 XOROUT V18 W14 Y3 for more information. ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Signal Ball Number Y7 Y13 Y15 Y17 M15 M18 M21 N9 N10 N12 N14 N16 P3 P6 P11 P13 ...
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... Intel E8870DH DDR Memory Hub (DMH) Datasheet Table 7-1 lists the signals needed for enabling the Signal I/O TSO I Tristate all outputs except XOROUT. XORIN I Input pin to the Parametric Tree. XOROUT O Output pin from the Parametric Tree. Table 7-2. Pin Names ...
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... BC0DQ[37] 129 BC0DQS[13] 130 BC0DQS[4] 131 BC0DQ[34] 132 BC0DQ[33] 133 BC0DQ[35] 134 BC0DQ[38] 135 BC0DQ[24] 136 ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Pin Names BC0DQ[28 BC0DQ[31] BC0DQ[29] BC0DQS[12] BC0DQS[3] BC0DQ[26] BC0DQ[25] BC0DQ[27] BC0DQ[30] BC0DQ[0] BC0DQ[4] BC0DQ[7] BC0DQ[5] BC0DQS[9] BC0DQS[0] ...
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... Intel E8870DH DDR Memory Hub (DMH) Datasheet Pin Names Pin Order BC0SCLK#[3] 180 BC0SCLK#[0] 181 BC0CS#[5] 182 BC0CS#[2] 183 BC0SCLK[0] 184 BC0CS#[7] 185 BC0CS#[3] ...
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... BC1DQ[33] 297 BC1DQ[35] 298 BC1DQ[38] 299 BC1DQ[24] 300 BC1DQ[28] 301 BC1DQ[31] BC1DQ[29] BC1DQS[12] BC1DQS[3] BC1DQ[26] ® Intel E8870DH DDR Memory Hub (DMH) Datasheet Pin Names BC1DQ[25] BC1DQ[27] BC1DQ[30] BC1DQ[56] BC1DQ[60] BC1DQ[63] BC1DQ[61] BC1DQS[16] BC1DQS[7] BC1DQ[58] BC1DQ[57] BC1DQ[59] BC1DQ[62] BC1DQ[48] BC1DQ[52] ...