MT45W2MW16PFA-70 Micron Technology Inc, MT45W2MW16PFA-70 Datasheet - Page 15

• Manufacturer Part Number: MT45W2MW16PFA-70
• Manufacturer: Micron Technology Inc

Specifications of MT45W2MW16PFA-70

• Lead Free Status / RoHS Status: Not Compliant

Figure 12:
Table 3:
Partial-Array Refresh (CR[2:0]) Default = Full Array Refresh
Sleep Mode (CR[4]) Default = PAR Enabled, DPD Disabled
PDF: 09005aef80be1ee8/Source: 09005aef80be1f7f
AsyncCellularRAM_2.fm - Rev. G 10/05 EN
CR[2]
0
0
0
0
1
1
1
1
CR[7]
0
1
CR[6] CR[5]
64Mb Address Patterns for PAR (CR[4] = 1)
1
1
0
0
Configuration Register Bit Mapping
CR[1]
All must be set to "0"
0
0
1
1
0
0
1
1
Page Mode Disabled (default)
Page Mode Enabled
1
0
1
0
Page Mode Enable/Disable
RESERVED
+70˚C
+45˚C
+15˚C
+85˚C (default)
Maximum Case Temp.
A[21:8]
21– 8
CR[0]
The PAR bits restrict refresh operation to a portion of the total memory array. This fea-
ture allows the system to reduce current by only refreshing that part of the memory array
required by the host system. The refresh options are full array, one-half array, one-quar-
ter array, one-eighth array, or none of the array. The mapping of these partitions can
start at either the beginning or the end of the address map (see Table 3).
The sleep mode bit determines which low-power mode is to be entered when ZZ# is
driven LOW. If CR[4] = 1, PAR operation is enabled. If CR[4] = 0, DPD operation is
enabled. PAR can also be enabled directly by writing to the CR using the software access
sequence. Note that this then disables ZZ# initiation of PAR. DPD cannot be enabled or
disabled using the software access sequence; this should only be done using ZZ# to
access the CR.
0
1
0
1
0
1
0
1
One-quarter of die
One-quarter of die
PAGE
One-eighth of die
One-eighth of die
Active Section
One-half of die
One-half of die
7
A7
None of die
64Mb: 4 Meg x 16 Async/Page CellularRAM 1.0 Memory
Full die
6
TCR
A6
5
A5
SLEEP
CR[4]
0
1
4
A4
15
Must be set to "0"
RESERVED
DPD Enabled
PAR Enabled (default)
000000h–3FFFFFh
000000h–1FFFFFh
000000h–0FFFFFh
000000h–07FFFFh
200000h–3FFFFFh
300000h–3FFFFFh
380000h–3FFFFFh
Address Space
3
A3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Sleep Mode
0
Configuration Register Operation
CR[2]
2
A2
0
0
0
0
1
1
1
1
CR[1] CR[0]
0
0
1
1
0
0
1
1
PAR
1
A1
0
1
0
1
0
1
0
1
4 Meg x 16
2 Meg x 16
1 Meg x 16
0 Meg x 16
2 Meg x 16
1 Meg x 16
512K x 16
512K x 16
Full array (default)
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
None of array
Top 1/2 array
Top 1/4 array
Top 1/8 array
Size
PAR Refresh Coverage
0
A0
©2003 Micron Technology, Inc. All rights reserved.
Configuration
Address Bus
Register
Density
64Mb
32Mb
16Mb
32Mb
16Mb
8Mb
0Mb
8Mb