SMC128CFB6E Micron Technology Inc, SMC128CFB6E Datasheet - Page 15

• Manufacturer Part Number: SMC128CFB6E
• Manufacturer: Micron Technology Inc
• Type: CompactFlashr

Specifications of SMC128CFB6E

• Density: 128MByte
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: Not Required
• Mounting: Socket
• Pin Count: 50
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.97/4.5V
• Operating Supply Voltage (max): 3.63/5.5V
• Programmable: Yes
• Lead Free Status / RoHS Status: Compliant

SMC128CF, SMC01GCF, SMC08GCF
Table 8.
RESET
(PC card memory mode)
RESET
(PC card I/O mode)
–RESET
(True IDE mode)
V
(PC card memory mode)
V
(PC card I/O mode)
V
(True IDE mode)
–VS1, –VS2
(PC card memory mode)
–VS1, –VS2
–VS1, –VS2
–WAIT
(PC card memory mode)
–WAIT
(PC card I/O mode)
IORDY
(True IDE mode - except
Ultra DMA mode)
-DDMARDY
(True IDE mode – Ultra
DMA Write mode)
DSTROBE
(True IDE mode – Ultra
DMA Read mode)
(PC card I/O mode)
(True IDE mode)
CC
CC
CC
Signal name
Signals description (continued)
Dir.
O
O
I
13,38
33,40
Pin
41
42
Resets the card (active High). The card is reset at power-up
only if this pin is left High or unconnected.
Same as PC card memory mode.
Hardware reset from the host (active Low).
+5 V, +3.3 V power.
Same for all modes.
Same for all modes.
Voltage sense signals.–VS1 is grounded so that the CIS
can be read at 3.3 volts and –VS2 is reserved by PCMCIA
for a secondary voltage.
Same for all modes.
Same for all modes.
Numonyx CF does not assert the WAIT (IORDY) signal
In True IDE mode, except in Ultra DMA mode, this output
signal may be used as IORDY.
In True IDE mode, when Ultra DMA mode DMA Write is
active, this signal is asserted by the host to indicate that the
device is read to receive Ultra DMA data-in bursts.
The device may negate -DDMARDY to pause an Ultra DMA
transfer.
In True IDE mode, when Ultra DMA mode DMA Write is
active, this signal is the data out strobe generated by the
device. Both the rising and falling edge of DSTROBE cause
data to be latched by the host. The device may stop
generating DSTROBE edges to pause an Ultra DMA data-
out burst.
Description
Electrical interface
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