CY7C4225-15ASC Cypress Semiconductor Corp, CY7C4225-15ASC Datasheet - Page 11

CY7C4225-15ASC

Manufacturer Part Number
CY7C4225-15ASC
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY7C4225-15ASC

Configuration
Dual
Density
18Kb
Access Time (max)
10ns
Word Size
18b
Organization
1Kx18
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
TQFP
Clock Freq (max)
66.7MHz
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (max)
5.5V
Supply Current
45mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
64
Lead Free Status / RoHS Status
Not Compliant
Switching Waveforms
Notes:
Document Number: 001-45652 Rev. **
19. t
20. The clocks (RCLK, WCLK) can be free-running during reset.
21. After reset, the outputs will be LOW if OE = 0 and three-state if OE = 1.
the rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
REN, WEN,
Q
0
EF,PAE
FF,PAF,
Q
WCLK
–Q
RCLK
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. It the time between
WEN
REN
0
–Q
OE
EF
17
RS
HF
LD
17
t
ENS
t
OLZ
(continued)
t
ENH
t
CLKH
t
t
A
REF
t
t
t
RSF
RSF
RSF
t
OE
t
RS
Figure 7. Read Cycle Timing
t
Figure 8. Reset Timing
CLK
t
SKEW2
NO OPERATION
SKEW2
[19]
t
CLKL
, then EF may not change state until the next RCLK edge.
[20]
VALID DATA
t
RSR
t
REF
t
OHZ
CY7C4425/4205/4215
CY7C4225/4235/4245
OE = 0
OE = 1
[21]
Page 11 of 22
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