CY7C4225-15AC Cypress Semiconductor Corp, CY7C4225-15AC Datasheet
CY7C4225-15AC
Specifications of CY7C4225-15AC
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CY7C4225-15AC Summary of contents
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... CY7C4425V /4205V/4215V CY7C4225V /4235V/4245V64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs 64/256/512/1K/2K/4K x18 Low-Voltage Synchronous FIFOs Features • 3.3V operation for low power consumption and easy integration into low-voltage systems • High-speed, low-power, first-in first-out (FIFO) memories • (CY7C4425V) • 256 x 18 (CY7C4205V) • 512 x 18 (CY7C4215V) • ...
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... WRITE RESET LOGIC THREE–STATE OUTPUT REGISTER LOGIC OE Q 0–17 STQFP/TQFP Top View CY7C4425V 6 CY7C4205V 7 CY7C4215V 8 CY7C4225V 9 10 CY7C4235V 11 CY7C4245V CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V FLAG PROGRAM REGISTER FF EF FLAG PAE LOGIC PAF SMODE READ POINTER READ CONTROL RCLK REN GND ...
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... FL is tied all devices. Not Cascaded – Tied function is also available in standalone mode by strobing RT. Cascaded – Connected to WXO of previous device. Not Cascaded – Tied to V Cascaded – Connected to RXO of previous device. Not Cascaded – Tied to V CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V CY7C42X5V-35 Unit 40 28.6 ...
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... Table 1. Write Offset Register LD WEN WCLK 0 0 0–17 outputs 0− outputs 0− CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V . CC . (Almost Empty SS during a program write will determine 0–11 is written into the Empty offset register on [1] Selection Writing to offset registers: Empty Offset Full Offset No Operation Write Into FIFO ...
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... Note Empty Offset (Default Values: CY7C4425V CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127 Full Offset (Default Values: CY7C4425V CY7C4205V n = 31, CY7C4215V n = 63, CY7C4225V/7C4235V/7C4245V n = 127). Document #: 38-06029 Rev. *C that the FIFO is either Almost Full or Almost Empty. See Table 2 for a description of programmable flags. ...
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... ORing together these respective flags for monitoring. The composite PAE and PAF flags are not precise. Document #: 38-06029 Rev. *C CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V ANDing the Empty (Full) flags of every FIFO. This technique will avoid ready data from the FIFO that is “staggered” by one clock cycle due to the variations in skew between RCLK and WCLK ...
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... DATAIN (D) FIRSTLOAD (FL) WRITECLOCK (WCLK) WRITE ENABLE (WEN) RESET(RS) LOAD (LD) FF PAF FIRSTLOAD (FL) Figure 2. Block Diagram of Low-Voltage Synchronous FIFO Memory with Programmable Flags used in Depth Expansion Configuration Document #: 38-06029 Rev. *C CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V WXO RXO 7C4425V 7C4205V 7C4215V 7C4225V 7C4235V V CC 7C4245V FF EF ...
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... WCLK and RCLK, which are switching at 20 MHz. 7. All inputs = Tested initially and after any design or process changes that may affect these parameters Document #: 38-06029 Rev. *C CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V DC Input Voltage .................................................... −0.5V to +5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) ° ...
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... Document #: 38-06029 Rev. *C [9, 10] 3. 510Ω GND ≤ Vth = 2.0V 7C42X5V-15 Min. Max [12 [12] 3 [13] /SMODE tied /SMODE tied [13] /SMODE tied /SMODE tied OHZ . PAF(E) CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V ALL INPUT PULSES 90% 90% 10% 10% ≤ 7C42X5V-25 7C42X5V-35 Min. Max. Min. Max. Unit 66.7 40 28.6 MHz ...
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... RCLK and the rising edge of WCLK is less than t Document #: 38-06029 Rev. *C 7C42X5V-15 Min. Max. 6 CLK t CLKL ENH t ENS t WFF , then FF may not change state until the next WCLK edge. SKEW1 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V 7C42X5V-25 7C42X5V-35 Min. Max. Min. Max. Unit ...
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... After reset, the outputs will be LOW and three-state Document #: 38-06029 Rev CLK t CLKL NO OPERATION t REF VALID DATA t OE [15] t SKEW2 RSR t RSF t RSF t RSF , then EF may not change state until the next RCLK edge. SKEW2 CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V REF t OHZ [17 Page [+] Feedback ...
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... REN OE Q – Notes: 18. When t > minimum specification, t (maximum SKEW2 FRL + t . The Latency Timing applies only at the Empty Boundary (EF = LOW). SKEW2 19. The first word is available the cycle after EF goes HIGH, always. Document #: 38-06029 Rev. *C CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V [18] t FRL t REF OLZ t OE ...
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... RCLK t ENH t ENS REN LOW –q DATA IN OUTPUT REGISTER 0 17 Half-Full Flag Timing- t CLKH WCLK WEN HALF FULL OR LESS HF RCLK REN Document #: 38-06029 Rev. *C CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V NO WRITE [14 SKEW1 DATA WRITE t WFF t ENS DATAREAD t CLKL t t ENS ENH t HF HALF FULL+1 OR MORE t ...
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... If a read is performed on this rising edge of the read clock, there will be Empty + (n−1) words in the FIFO when PAE goes LOW. Document #: 38-06029 Rev CLKL t t ENS ENH t PAE t ENS t CLKL t ENS ENH Note 21 t [22] PAEsynch t ENS CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V n+1 WORDS n WORDS IN FIFO IN FIFO t PAE WORDS Note 23 INFIFO t PAEsynch t t ENS ENH Page [+] Feedback ...
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... CY7C4425V, 256 – m words inCY7C4205V, 512 − m words in CY7C4215V. 1024 – m words in CY7C4225V, 2048 − m words in CY7C4235V, and 4096 – m words in CY7C4245V. 27. 64 − words in CY7C4425V, 256 − words in CY7C4205V, 512 − words in CY7C4215V, 1024 − CY7C4225V, 2048 − CY74235V, and 4096 − words in CY7C4245V. ...
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... CLKH RCLK t ENS LD t ENS REN Q – Write Expansion Out Timing t CLKH WCLK WXO t ENS WEN Note: 31. Write to Last Physical Location. Document #: 38-06029 Rev. *C CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V t CLKL t ENH t DH PAF OFFSET t CLKL t ENH t A UNKNOWN PAE OFFSET Note PAE OFFSET D –D ...
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... The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at t 35. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after t Document #: 38-06029 Rev. *C Note XIS t PRT RTR CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V XIS t RTR . RTR to update these flags. Page [+] Feedback ...
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... Low-Voltage Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4215V-15ASC CY7C4215V-15ASXC 25 CY7C4215V-25ASC 35 CY7C4215V-35ASC Low-Voltage Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4225V-15ASC CY7C4225V-15ASXC CY7C4225V-15AC 25 CY7C4225V-25ASC 35 CY7C4225V-35ASC Low-Voltage Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4235V-15ASC CY7C4235V-15ASXC 25 CY7C4235V-25ASC 35 CY7C4235V-35ASC Low-Voltage Synchronous FIFO Speed (ns) Ordering Code 15 CY7C4245V-15ASC CY7C4245V-15ASXC 25 CY7C4245V-25ASC CY7C4245V-25ASXC ...
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... The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. CY7C4225V/4205V/4215V CY7C4425V/4235V/4245V ...
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... Document History Page Document Title: CY7C4425V/4205V/4215V CY7C4225V/4235V/4245V 64/256/512/1K/2K/ Low-Voltage Synchro- nous FIFOs Document Number: 38-06029 REV. ECN NO. Issue Date ** 109961 12/17/01 *A 122281 12/26/02 *B 127856 08/22/03 *C 393636 See ECN Document #: 38-06029 Rev. *C Orig. of Change Description of Change SZV Change from Spec number: 38-00609 to 38-06029 ...