AM27C040-150DC AMD (ADVANCED MICRO DEVICES), AM27C040-150DC Datasheet - Page 5

• Manufacturer Part Number: AM27C040-150DC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM27C040-150DC

• Density: 4Mb
• Access Time (max): 150ns
• Supply Current: 40mA
• Pin Count: 32
• Mounting: Through Hole
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Supplier Unconfirmed

FUNCTIONAL DESCRIPTION
Device Erasure
In order to clear all locations of their programmed
contents, the device must be exposed to an ultraviolet
light source. A dosage of 15 W seconds/cm
to completely erase the device. This dosage can be ob-
tained by exposure to an ultraviolet lamp — wavelength
of 2537 Å — with intensity of 12,000 µW/cm
minutes. The device should be directly under and about
one inch from the source and all filters should be re-
moved from the UV light source prior to erasure.
Note that all UV erasable devices will erase with light
sources having wavelengths shorter than 4000 Å, such
as fluorescent light and sunlight. Although the erasure
process happens over a much longer time period, ex-
posure to any light source should be prevented for
maximum system reliability. Simply cover the package
window with an opaque label or substance.
Device Programming
Upon delivery, or after each erasure, the device has
all of its bits in the “ONE”, or HIGH state. “ZEROs” are
loaded into the device through the programming pro-
cedure.
The programming mode is entered when 12.75 V
0.25 V is applied to the V
and OE# is at V
For programming, the data to be programmed is ap-
plied 8 bits in parallel to the data output pins.
The flowchart in the EPROM Products Data Book, Pro-
gramming section (Section 5, Figure 5-1) shows AMD’s
Flashrite algorithm. The Flashrite algorithm reduces pro-
gramming time by using a 100 µs programming pulse
and by giving each address only as many pulses to reli-
ably program the data. After each pulse is applied to a
given address, the data in that address is verified. If the
data does not verify, additional pulses are given until it
verifies or the maximum pulses allowed is reached. This
process is repeated while sequencing through each ad-
dress of the device. This part of the algorithm is done at
V
grammed to a sufficiently high threshold voltage. After
the final address is completed, the entire EPROM mem-
ory is verified at V
Please refer to the EPROM Products Data Book, Sec-
tion 5 for the programming flow chart and characteris-
tics.
Program Inhibit
Programming different data to multiple devices in par-
allel is easily accomplished. Except for CE#/PGM#, all
like inputs of the devices may be common. A TTL
low-level program pulse applied to one device’s CE#/
PGM# input with V
CC
= 6.25 V to assure that each EPROM bit is pro-
IH
CC
.
PP
= V
= 12.75 V
PP
PP
= 5.25 V.
pin, CE#/PGM# is at V
0.25 V will program
2
2
for 15 to 20
is required
F I N A L
Am27C040
IL
that particular device. A high-level CE#/PGM# input in-
hibits the other devices from being programmed.
Program Verify
A verification should be performed on the programmed
bits to determine that they were correctly programmed.
The verify should be performed with OE# at V
PGM# at V
Auto Select Mode
The autoselect mode provides manufacturer and de-
vice identification through identifier codes on DQ0–
DQ7. This mode is primarily intended for programming
equipment to automatically match a device to be pro-
grammed with its corresponding programming algo-
rithm. This mode is functional in the 25 C
ambient temperature range that is required when pro-
gramming the device.
To activate this mode, the programming equipment
must force V
may then be sequenced from the device outputs by tog-
gling address line A0 from V
the address from 00h to 01h). All other address lines
must be held at V
Byte 0 (A0 = V
and Byte 1 (A0 = V
codes have odd parity, with DQ7 as the parity bit.
Read Mode
To obtain data at the device outputs, Chip Enable (CE#/
PGM#) and Output Enable (OE#) must be driven low.
CE#/PGM# controls the power to the device and is typ-
ically used to select the device. OE# enables the device
to output data, independent of device selection. Ad-
dresses must be stable for at least t
the Switching Waveforms section for the timing dia-
gram.
Standby Mode
The device enters the CMOS standby mode when
CE#/PGM# is at V
reduced to 100 µA. The device enters the TTL-standby
mode when CE#/PGM# is at V
rent is reduced to 1.0 mA. When in either standby
mode, the device places its outputs in a high-imped-
ance state, independent of the OE# input.
Output OR-Tieing
To accommodate multiple memory connections, a
two-line control function is provided to allow for:
CE#/PGM# should be decoded and used as the pri-
mary device-selecting function, while OE# be made a
Low memory power dissipation, and
Assurance that output bus contention will not occur
IH
H
, and V
on address line A9. Two identifier bytes
IL
) represents the manufacturer code,
IL
CC
IH
during the autoselect mode.
PP
), the device identifier code. Both
between 12.5 V and 13.0 V.
0.3 V. Maximum V
IL
to V
IH
. Maximum V
IH
ACC
(that is, changing
–t
CC
OE
. Refer to
current is
IL
CC
, CE#/
5 C
cur-
5