IS42S32200B7TL ISSI, Integrated Silicon Solution Inc, IS42S32200B7TL Datasheet
IS42S32200B7TL
Specifications of IS42S32200B7TL
Related parts for IS42S32200B7TL
IS42S32200B7TL Summary of contents
Page 1
... September 2003 OVERVIEW ISSI 's 64Mb Synchronous DRAM IS42S32200B is organized as 524,288 bits x 32-bit x 4-bank for improved performance. The synchronous DRAMs achieve high- speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATION ...
Page 2
... IS42S32200B GENERAL DESCRIPTION The 64Mb SDRAM is a high speed CMOS, dynamic random-access memory designed to operate in 3.3V memory systems containing 67,108,864 bits. Internally configured as a quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 2,048 rows by 256 columns by 32 bits. The 64Mb SDRAM includes an AUTO REFRESH MODE, and a power-saving, power-down mode ...
Page 3
IS42S32200B PIN FUNCTIONS Symbol Pin No. Type A0-A10 Input Pin BA0, BA1 22,23 Input Pin CAS 18 Input Pin CKE 67 Input Pin CLK 68 Input Pin CS 20 Input Pin DQ0 to ...
Page 4
... LOW, the corresponding buffer byte is enabled, and when HIGH, disabled. The outputs go to the HIGH Impedance State when DQMx is HIGH. This function corresponds conventional DRAMs. In write mode, DQMx control the input buffer. When DQMx is LOW, the corresponding buffer byte is enabled, and data can be written to the device. ...
Page 5
... During the SELF REFRESH operation, the row address to be refreshed, the bank, and the refresh interval are generated automatically internally. SELF REFRESH can be used to retain data in the SDRAM without external clocking, even if the rest of the system is powered down. The SELF REFRESH operation is started by dropping the CKE pin from HIGH to LOW. During the SELF REFRESH operation all other inputs to the SDRAM become “ ...
Page 6
IS42S32200B TRUTH TABLE – COMMANDS AND DQM OPERATION FUNCTION COMMAND INHIBIT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank/column, start READ burst) WRITE (Select bank/column, start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank ...
Page 7
... NOTES: 1. CKEn is the logic state of CKE at clock edge n ; CKEn-1 was the state of CKE at the previous clock edge. 2. Current state is the state of the SDRAM immediately prior to clock edge COMMANDn is the command registered at clock edge n , and ACTONn is a result of COMMANDn. 4. All states and sequences not shown are illegal or reserved. ...
Page 8
... Accessing Mode Register: Starts with registration of a LOAD MODE REGISTER command and ends when met, the SDRAM will be in the all banks idle state. MRD Precharging All: Starts with registration of a PRECHARGE ALL command and ends when t banks will be in the idle state. ...
Page 9
IS42S32200B TRUTH TABLE – CURRENT STATE BANK n, COMMAND TO BANK m CURRENT STATE COMMAND (ACTION) Any COMMAND INHIBIT (NOP/Continue previous operation) NO OPERATION (NOP/Continue previous operation) Any Command Otherwise Allowed to Bank m Idle Row ACTIVE (Select and activate ...
Page 10
IS42S32200B 7. READs or WRITEs to bank m listed in the Command (Action) column include READs or WRITEs with auto precharge enabled and READs or WRITEs with auto precharge disabled. 8. CONCURRENT AUTO PRECHARGE: Bank n will initiate the AUTO ...
Page 11
... IS42S32200B FUNCTIONAL DESCRIPTION The 64Mb SDRAMs 512K banks) are quad-bank DRAMs which operate at 3.3V and include a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 16,777,216-bit banks is organized as 2,048 rows by 256 columns by 32bits. Read and write accesses to the SDRAM are burst oriented; ...
Page 12
... IS42S32200B REGISTER DEFINITION Mode Register The mode register is used to define the specific mode of operation of the SDRAM. This definition includes the selection of a burst length, a burst type, a CAS\ latency, an operating mode and a write burst mode, as shown in MODE REGISTER DEFINITION. The mode register is programmed via the LOAD MODE ...
Page 13
... IS42S32200B Burst Length Read and write accesses to the SDRAM are burst ori- ented, with the burst length being programmable, as shown in MODE REGISTER DEFINITION. The burst length determines the maximum number of column loca- tions that can be accessed for a given READ or WRITE command. Burst lengths locations are ...
Page 14
IS42S32200B CAS Latency The CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first piece of output data. The latency can be set to two or three clocks. If ...
Page 15
... OPERATION BANK/ROW ACTIVATION Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be “opened.” This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated (see Activating Specific Row Within Specific Bank). ...
Page 16
... READ burst, provided that DQ contention can be avoided given system design, there may be a possibility that the device driving the input data will go Low-Z before the SDRAM DQs go High-Z. In this case, at least a single-cycle delay should occur between the last read data and the WRITE command. ...
Page 17
IS42S32200B same bank. The PRECHARGE command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the CAS latency minus one. This is shown in the READ to PRECHARGE ...
Page 18
IS42S32200B Consecutive READ Bursts T0 CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - NOP NOP NOP ...
Page 19
IS42S32200B Random READ Accesses T0 CLK COMMAND READ BANK, ADDRESS COL CLK COMMAND READ BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — www.issi.com — ...
Page 20
IS42S32200B RW1 - READ to WRITE CLK DQM COMMAND ADDRESS DQ RW2 - READ to WRITE With Extra Clock Cycle T0 CLK DQM COMMAND READ BANK, ADDRESS COL READ NOP NOP BANK, COL ...
Page 21
IS42S32200B READ to PRECHARGE T0 T1 CLK COMMAND READ NOP BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - 3 Integrated Silicon Solution, Inc. — ...
Page 22
IS42S32200B READ Burst Termination T0 CLK COMMAND READ BANK a, ADDRESS COL n DQ CAS Latency - CLK COMMAND READ NOP BANK, ADDRESS COL n DQ CAS Latency - BURST NOP ...
Page 23
... An example is shown in WRITE to WRITE diagram. Data either the last of a burst of two or the last desired of a longer burst. The 64Mb SDRAM uses a pipelined architecture and therefore does not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command ...
Page 24
IS42S32200B WRITE Burst COMMAND ADDRESS Burst length = 2 DQM ix low. WRITE to WRITE DQMx is low. Each Write Command may be to any bank. Random WRITE Cycles COMMAND ADDRESS DQMx is low. Each Write Command may be to ...
Page 25
IS42S32200B WRITE to READ T0 CLK COMMAND WRITE BANK, ADDRESS COL WRITE to PRECHARGE ( CLK DQM COMMAND WRITE BANK a, ADDRESS COL Integrated Silicon Solution, Inc. — www.issi.com ...
Page 26
IS42S32200B WRITE to PRECHARGE ( CLK DQM WRITE COMMAND BANK a, ADDRESS COL WRITE Burst Termination COMMAND ADDRESS 26 2 CLK ( NOP NOP PRECHARGE BANK ...
Page 27
IS42S32200B PRECHARGE The PRECHARGE command (see figure) is used to deactivate the open row in a particular bank or the open row in all banks. The bank(s) will be available for a subsequent row access some specified time (t the ...
Page 28
IS42S32200B CLOCK SUSPEND Clock suspend mode occurs when a column access/burst is in progress and CKE is registered LOW. In the clock suspend mode, the internal clock is deactivated, “freezing” the synchronous logic. For each positive clock edge on which ...
Page 29
... CONCURRENT AUTO PRECHARGE An access command (READ or WRITE) to another bank while an access command with auto precharge enabled is executing is not allowed by SDRAMs, unless the SDRAM supports CONCURRENT AUTO PRECHARGE. ISSI Fig CAP 1 - READ With Auto Precharge interrupted by a READ T0 ...
Page 30
IS42S32200B WRITE with Auto Precharge 3. Interrupted by a READ (with or without auto precharge): A READ to bank m will interrupt a WRITE on bank n when registered, with the data-out appearing CAS latency later. The PRECHARGE to bank ...
Page 31
IS42S32200B ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage DD MAX V Maximum Supply Voltage for Output Buffer DDQ MAX V Input Voltage IN V Output Voltage OUT P Allowable Power Dissipation D MAX I Output Shorted Current CS ...
Page 32
IS42S32200B DC ELECTRICAL CHARACTERISTICS Input Leakage Current IL I Output Leakage Current OL V Output High Voltage Level OH V Output Low Voltage Level ...
Page 33
IS42S32200B AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Clock Cycle Time CK3 t CK2 t Access Time From CLK (4) AC3 t AC2 t CLK HIGH Level Width CHI t CLK LOW Level Width CL t Output Data Hold Time OH ...
Page 34
IS42S32200B AC ELECTRICAL CHARACTERISTICS Symbol Parameter t Input Data To Precharge DPL3 Command Delay time t DPL2 Input Data To Active / Refresh CAS Latency = 3 t DAL3 Command Delay time (During Auto-Precharge) t DAL2 t Transition Time (2) ...
Page 35
IS42S32200B OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t READ/WRITE command to READ/WRITE command CCD t CKE to clock disable or power-down entry mode CKED t CKE to clock enable or power-down exit ...
Page 36
IS42S32200B INITIALIZE AND LOAD MODE REGISTER CLK CKS CKH CKE CMH CMS CMH CMS COMMAND NOP PRECHARGE DQM0-DQM3 A0-A9 ALL BANKS A10 SINGLE BANK BA0, BA1 ALL BANKS DQ T ...
Page 37
IS42S32200B POWER-DOWN MODE CYCLE T0 CLK t t CKS CKH CKE t t CMS CMH COMMAND PRECHARGE DQM0-DQM3 A0-A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK DQ High-Z All banks idle, enter Precharge all active ...
Page 38
IS42S32200B CLOCK SUSPEND MODE CLK CKS CKH CKS CKE t t CMS CMH COMMAND READ NOP t t CMS CMH DQM0-DQM3 A0-A9 (2) COLUMN ...
Page 39
IS42S32200B AUTO-REFRESH CYCLE CLK t t CKS CKH CKE t t CMS CMH PRECHARGE NOP COMMAND DQM0-DQM3 A0-A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK ( High-Z CAS latency = 2, ...
Page 40
IS42S32200B SELF-REFRESH CYCLE T0 t CLK CKS CKH CKE t t CMS CMH COMMAND PRECHARGE NOP DQM0-DQM3 A0-A9 ALL BANKS A10 SINGLE BANK BA0, BA1 BANK DQ High-Z t Precharge all active banks ...
Page 41
IS42S32200B READ WITHOUT AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW t t DISABLE AUTO PRECHARGE ...
Page 42
IS42S32200B READ WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW ENABLE AUTO PRECHARGE A10 ROW t t ...
Page 43
IS42S32200B SINGLE READ WITHOUT AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW ...
Page 44
IS42S32200B SINGLE READ WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9, ROW A10 ROW ...
Page 45
IS42S32200B ALTERNATING BANK READ ACCESSES CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW ENABLE AUTO PRECHARGE A10 ROW t t ...
Page 46
IS42S32200B READ - FULL-PAGE BURST CLK CKS CKH CKE t t CMS CMH COMMAND ACTIVE NOP READ t CMS DQM0-DQM3 A0-A9, ROW COLUMN ...
Page 47
IS42S32200B READ - DQM OPERATION CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW BA0, ...
Page 48
IS42S32200B WRITE - WITHOUT AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW t t DISABLE AUTO ...
Page 49
IS42S32200B WRITE - WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND t CMS DQM0-DQM3 A0-A9 ROW ENABLE AUTO PRECHARGE ...
Page 50
IS42S32200B SINGLE WRITE - WITHOUT AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW t t DISABLE ...
Page 51
IS42S32200B SINGLE WRITE - WITH AUTO PRECHARGE CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW t ...
Page 52
IS42S32200B ALTERNATING BANK WRITE ACCESS CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND t CMS DQM0-DQM3 A0-A9 ROW ENABLE AUTO PRECHARGE A10 ...
Page 53
IS42S32200B WRITE - FULL PAGE BURST CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW ...
Page 54
IS42S32200B WRITE - DQM OPERATION CLK t t CKS CKH CKE t t CMS CMH ACTIVE NOP COMMAND DQM0-DQM3 A0-A9 ROW A10 ROW BA0, ...
Page 55
IS42S32200B ORDERING INFORMATION Commercial Range Frequency Speed (ns) 166 MHz 6 166 MHz 6 143 MHz 7 143 MHz 7 Industrial Range: - Frequency Speed (ns) 166 MHz 6 166 MHz ...
Page 56
PACKAGING INFORMATION Plastic TSOP 54–Pin, 86-Pin Package Code: T (Type II Plastic TSOP (T - Type II) Millimeters Symbol Min Max Ref. Std. No. Leads ( — 1.20 A1 0.05 0.15 A2 — ...