K4H561638F-ULB3 Samsung Semiconductor, K4H561638F-ULB3 Datasheet - Page 18

• Manufacturer Part Number: K4H561638F-ULB3
• Manufacturer: Samsung Semiconductor
• Type: DDR SDRAMr

Specifications of K4H561638F-ULB3

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 200mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

DDR SDRAM 256Mb F-die (x8, x16) Pb-Free
Component Notes
10. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this
11. tQH = tHP - tQHS, where:
12. tDQSQ
13. tDAL = (tWR/tCK) + (tRP/tCK)
System Notes :
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 1.
1. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. these parameters are not referenced to a
2. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys
3. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A
4. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device.
5. For command/address input slew rate ≥ 1.0 V/ns
6. For command/address input slew rate ≥ 0.5 V/ns and < 1.0 V/ns
7. For CK & CK slew rate ≥ 1.0 V/ns
8. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by
9. Slew Rate is measured between VOH(ac) and VOL(ac).
specific voltage level but specify when the device output in no longer driving (HZ), or begins driving (LZ).
be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS.
device design or tester correlation.
ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could
Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle.
tem performance (bus turnaround) will degrade accordingly.
valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ
value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the
period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into
the clock traces.
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The
case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p-
channel to n-channel variation of the output drivers.
For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and
tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3)
tDAL = 5 clocks
pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst
Output
Figure 1 : Pullup slew rate test load
VSSQ
50
Ω
Test point
Rev. 1.2 October, 2004
DDR SDRAM