K4H561638F-ULB3 Samsung Semiconductor, K4H561638F-ULB3 Datasheet - Page 15

• Manufacturer Part Number: K4H561638F-ULB3
• Manufacturer: Samsung Semiconductor
• Type: DDR SDRAMr

Specifications of K4H561638F-ULB3

• Organization: 16Mx16
• Density: 256Mb
• Address Bus: 15b
• Access Time (max): 700ps
• Maximum Clock Rate: 333MHz
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 200mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

AC Timming Parameters & Specifications
DDR SDRAM 256Mb F-die (x8, x16) Pb-Free
Row cycle time
Refresh row cycle time
Row active time
RAS to CAS delay
Row precharge time
Row active to Row active delay
Write recovery time
Last data in to Read command
Col. address to Col. address delay
Clock cycle time
Clock high level width
Clock low level width
DQS-out access time from CK/CK
Output data access time from CK/CK
Data strobe edge to ouput data edge
Read Preamble
Read Postamble
CK to valid DQS-in
DQS-in setup time
DQS-in hold time
DQS falling edge to CK rising-setup time
DQS falling edge from CK rising-hold time
DQS-in high level width
DQS-in low level width
DQS-in cycle time
Address and Control Input setup time(fast)
Address and Control Input hold time(fast)
Address and Control Input setup time(slow)
Address and Control Input hold time(slow)
Data-out high impedence time from CK/CK
Data-out low impedence time from CK/CK
Output Slew Rate Matching Ratio(rise to fall)
Parameter
CL=2.0
CL=2.5
tWPRES
tDQSCK
Symbol
tWPRE
tDQSQ
tDQSS
tDQSH
tRPRE
tDQSL
tSLMR
tRPST
tWTR
tRCD
tRRD
tCCD
tDSH
tDSC
tRFC
tRAS
tDSS
tWR
tRC
tRP
tCK
tCH
tAC
tCL
tHZ
tLZ
tIS
tIH
tIS
tIH
(DDR333@CL=2.5)
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.75
0.75
0.67
-0.6
-0.7
-0.7
-0.7
0.2
0.9
7.5
0.9
0.4
0.2
0.8
0.8
60
72
18
18
12
15
42
1
1
6
0
-
B3
Max
0.55
0.55
+0.6
+0.7
1.25
+0.7
+0.7
0.45
70K
1.1
0.6
1.1
1.5
12
12
(DDR266@CL=2.0)
-0.75
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
7.5
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
60
75
45
15
15
15
15
1
1
0
-
AA
+0.75
+0.75
120K
+0.75
+0.75
Max
0.55
0.55
1.25
1.1
0.6
1.1
1.5
0.5
12
12
(DDR266@CL=2.0)
-0.75
-0.75
-0.75
-0.75
Min
0.45
0.45
0.75
0.25
0.35
0.35
0.67
7.5
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
65
75
45
20
20
15
15
1
1
0
-
A2
Rev. 1.2 October, 2004
+0.75
+0.75
120K
Max
+0.75
+0.75
0.55
0.55
1.25
0.5
1.1
0.6
1.1
1.5
12
12
(DDR266@CL=2.5) Unit
-0.75
-0.75
-0.75
-0.75
0.75
0.25
0.35
Min
0.45
0.45
0.35
0.67
7.5
0.9
0.4
0.2
0.2
0.9
0.9
0.9
1.0
1.0
65
75
45
20
20
15
15
10
1
1
0
-
DDR SDRAM
B0
+0.75
+0.75
120K
+0.75
+0.75
Max
0.55
0.55
1.25
0.5
1.1
0.6
1.1
1.5
12
12
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
i,5.7
i,5.7
12
3
i,
i,
1
1