IC42S16100E7TL ISSI, Integrated Silicon Solution Inc, IC42S16100E7TL Datasheet
IC42S16100E7TL
Specifications of IC42S16100E7TL
Related parts for IC42S16100E7TL
IC42S16100E7TL Summary of contents
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... ISSI ’s 16Mb Synchronous DRAM IS42S16100E/ IC42S16100E is organized as a 524,288-word x 16-bit x 2-bank for improved performance. The synchronous DRAMs achieve high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. PIN CONFIGURATIONS 50-Pin TSOP (Type II) ...
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IS42S16100E, IC42S16100E PIN CONFIGURATION PACKAGE CODE BALL FBGA (Top View) (10 6.4 mm Body, 0.65 mm Ball Pitch PIN DESCRIPTIONS A0-A10 ...
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... HIGH, disabled. The outputs go the HIGH impedance state when LDQM/UDQM is HIGH. This function corresponds conventional DRAMs. In write mode, LDQM and UDQM control the input buffer. When LDQM or UDQM is LOW, the corresponding buffer byte is enabled, and data can be written to the device ...
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IS42S16100E, IC42S16100E FUNCTIONAL BLOCK DIAGRAM CLK CKE COMMAND CS DECODER RAS CAS & WE CLOCK MODE A11 GENERATOR REGISTER 11 A10 SELF A9 REFRESH REFRESH A8 CONTROLLER CONTROLLER A7 A6 REFRESH A5 COUNTER ROW ADDRESS ...
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IS42S16100E, IC42S16100E ABSOLUTE MAXIMUM RATINGS Symbol Parameters V Maximum Supply Voltage dd max V Maximum Supply Voltage for Output Buffer ddq max V Input Voltage iN V Output Voltage out P Allowable Power Dissipation d max I output Shorted Current ...
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IS42S16100E, IC42S16100E DC ELECTRICAL CHARACTERISTICS Symbol Parameter i Input Leakage Current il i Output Leakage Current ol V Output High Voltage Level Output Low Voltage Level Operating Current (1,2) cc1 i Precharge Standby Current ...
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IS42S16100E, IC42S16100E AC CHARACTERISTICS (1,2,3) Symbol Parameter t 3 Clock Cycle Time Access Time From CLK ( CLK HIGH Level Width chi t CLK LOW Level Width cl t ...
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IS42S16100E, IC42S16100E OPERATING FREQUENCY / LATENCY RELATIONSHIPS SYMBOL PARAMETER — Clock Cycle Time — Operating Frequency t CAS Latency cac t Active Command To Read/Write Command Delay Time rcd t RAS Latency ( rac rcd cac t ...
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IS42S16100E, IC42S16100E COMMANDS Active Command CLK CKE HIGH CS RAS CAS WE A0-A9 ROW A10 ROW BANK 1 A11 BANK 0 Write Command CLK HIGH CKE CS RAS CAS WE A0-A9 COLUMN AUTO PRECHARGE A10 NO PRECHARGE BANK 1 A11 ...
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IS42S16100E, IC42S16100E COMMANDS (cont.) No-Operation Command CLK CKE HIGH CS RAS CAS WE A0-A9 A10 A11 Mode Register Set Command CLK HIGH CKE CS RAS CAS WE A0-A9 OP-CODE A10 OP-CODE A11 OP-CODE 10 Device Deselect Command CLK CKE HIGH ...
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IS42S16100E, IC42S16100E COMMANDS (cont.) Self-Refresh Command CLK CKE CS RAS CAS WE A0-A9 A10 A11 Clock Suspend Command CLK CKE BANK(S) ACTIVE CS NOP RAS NOP CAS NOP WE NOP A0-A9 A10 A11 Integrated Silicon Solution, Inc. — www.issi.com Rev. ...
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... This command selects one of the two banks according to the A11 pin and activates the row selected by the pins A0 to A10. This command corresponds to the fall of the RAS signal from HIGH to LOW in conventional DRAMs. Precharge Command (CS, RAS LOW, CAS = HIGH) This command starts precharging the bank selected by pins A10 and A11 ...
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IS42S16100E, IC42S16100E Self-Refresh Command (CS, RAS, CAS, CKE = LOW HIGH) This command executes the self-refresh operation. The row address to be refreshed, the bank, and the refresh interval are generated automatically internally during this operation. The self-refresh ...
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IS42S16100E, IC42S16100E COMMAND TRUTH TABLE (1,2) Symbol Command MRS Mode Register Set (3,4) REF Auto-Refresh (5) SREF Self-Refresh (5,6) PRE Precharge Selected Bank PALL Precharge Both Banks ACT Bank Activate (7) WRIT Write WRITA Write With Auto-Precharge READ Read (8) ...
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IS42S16100E, IC42S16100E OPERATION COMMAND TABLE Current State Command Operation Idle DESL No Operation or Power-Down NOP No Operation or Power-Down BST No Operation or Power-Down READ / READA Illegal WRIT/WRITA Illegal ACT Row Active PRE/PALL No Operation REF/SELF Auto-Refresh or ...
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IS42S16100E, IC42S16100E OPERATION COMMAND TABLE Current State Command Operation Write With DESL Burst Write Continues, Write Recovery And Precharge Auto-Precharge When Done NOP Burst Write Continues, Write Recovery And Precharge BST Illegal READ/READA Illegal WRIT/WRITA Illegal Illegal (10) ACT Illegal ...
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IS42S16100E, IC42S16100E OPERATION COMMAND TABLE Current State Command Operation Write Recovery DESL No Operation, Idle State After t With Auto- NOP No Operation, Idle State After t Precharge BST No Operation, Idle State After t READ/READA Illegal WRIT/WRITA Illegal ACT ...
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IS42S16100E, IC42S16100E CKE RELATED COMMAND TRUTH TABLE Current State Operation Self-Refresh Undefined Self-Refresh Recovery Self-Refresh Recovery Illegal (2) Illegal (2) Self-Refresh Self-Refresh Recovery Idle State After t Idle State After t Illegal Illegal Power-Down on the Next Cycle Power-Down on ...
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IS42S16100E, IC42S16100E TWO BANKS OPERATION COMMAND TRUTH TABLE Operation CS RAS CAS WE A11 A10 A9-A0 DESL NOP BST READ/READA WRIT/WRITA ACT ...
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IS42S16100E, IC42S16100E SIMPLIFIED STATE TRANSITION DIAGRAM WRIT CKE_ CKE CLOCK WRITA SUSPEND CKE_ CKE POWER APPLIED Automatic transition following the completion of command execution. Transition due to command input. 20 (One Bank Operation) SREF entry MRS MODE REF IDLE REGISTER ...
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... IS42S16100E, IC42S16100E Device Initialization At Power-On (Power-On Sequence the case with conventional DRAMs, the IS42S16100E/ IC42S16100E product must be initialized by executing a stipulated power-on sequence after power is applied. After power is applied and Vdd and VddQ reach their stipulated voltages, set and hold the CKE and DQM pins HIGH for 100 µ ...
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IS42S16100E, IC42S16100E MODE REGISTER A11 A10 WRITE MODE LT MODE M11 M10 Note: Other values for these bits are reserved. 22 Address Bus ...
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IS42S16100E, IC42S16100E BURST LENGTH AND COLUMN ADDRESS SEQUENCE Column Address Burst Length ...
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IS42S16100E, IC42S16100E BANK SELECT AND PRECHARGE ADDRESS ALLOCATION Row X0 — X1 — X2 — X3 — X4 — X5 — X6 — X7 — X8 — X9 — X10 0 1 Command) X11 0 1 Column Y0 — Y1 ...
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IS42S16100E, IC42S16100E Burst Read The read cycle is started by executing the read command. The address provided during read command execution is used as the starting address. First, the data corresponding to this address is output in synchronization with the ...
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IS42S16100E, IC42S16100E Read With Auto-Precharge The read with auto-precharge command first executes a burst read operation and then puts the selected bank in the precharged state automatically. After the precharge completes, the bank goes to the idle state. Thus this ...
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IS42S16100E, IC42S16100E Write With Auto-Precharge The write with auto-precharge command first executes a burst write operation and then puts the selected bank in the precharged state automatically. After the precharge completes the bank goes to the idle state. Thus this ...
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IS42S16100E, IC42S16100E Interval Between Read Command A new command can be executed while a read cycle is in progress, i.e., before that cycle completes. When the second read command is executed, after the CAS latency has elapsed, data corresponding to ...
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IS42S16100E, IC42S16100E Interval Between Write and Read Commands A new read command can be executed while a write cycle is in progress, i.e., before that cycle completes. Data corresponding to the new read command is output after the CAS latency ...
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IS42S16100E, IC42S16100E Interval Between Read and Write Commands A read command can be interrupted and a new write command executed while the read cycle is in progress, i.e., before that cycle completes. Data corresponding to the new write command can ...
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IS42S16100E, IC42S16100E Precharge The precharge command sets the bank selected by pin A11 to the precharged state. This command can be executed at a time t following the execution of an active ras command to the same bank. The selected ...
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IS42S16100E, IC42S16100E Write Cycle Interruption Using the Precharge Command A write cycle can be interrupted by the execution of the precharge command before that cycle completes. The delay time (t ) from the precharge command to the point wdl where ...
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IS42S16100E, IC42S16100E Read Cycle (Full Page) Interruption Using the Burst Stop Command The IS42S16100E/IC42S16100E can output data continuously from the burst start address (a) to location a+255 during a read cycle in which the burst length is set to full ...
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IS42S16100E, IC42S16100E Write Cycle (Full Page) Interruption Using the Burst Stop Command The IS42S16100E/IC42S16100E can input data continuously from the burst start address (a) to location a+255 during a write cycle in which the burst length is set to full ...
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IS42S16100E, IC42S16100E Burst Data Interruption U/LDQM Pins (Write Cycle) Burst data input can be temporarily interrupted (muted ) during a write cycle using the U/LDQM pins. Regardless of the CAS latency, as soon as one of the U/LDQM pins goes ...
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IS42S16100E, IC42S16100E Bank Active Command Interval When the selected bank is precharged, the period trp has elapsed and the bank has entered the idle state, the bank can be activated by executing the active command. If the other bank is ...
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IS42S16100E, IC42S16100E OPERATION TIMING EXAMPLE Power-On Sequence, Mode Register Set Cycle CLK t CHI HIGH CKE RAS CAS t t ...
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IS42S16100E, IC42S16100E Power-Down Mode Cycle CLK t CHI CKS CK CL CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Auto-Refresh Cycle CLK t CHI CKS CK CL CKE RAS CAS A0- ...
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IS42S16100E, IC42S16100E Self-Refresh Cycle CLK t CHI CKS CK CL CKE t CKA RAS CAS A0-A9 ...
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IS42S16100E, IC42S16100E Read Cycle CLK t CHI CKS CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Auto-Precharge CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Full Page CLK t CHI t t CKS CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Ping-Pong Operation (Bank Switching CLK t CHI t t CKS CKE t CKA RAS CAS t ...
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IS42S16100E, IC42S16100E Write Cycle CLK t CHI CKS CK CL CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Auto-Precharge CLK t CHI CKS CK CL CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Full Page CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Ping-Pong Operation CLK t CHI t t CKS CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Page Mode CLK t CHI CKS CK CL CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Page Mode; Data Masking CLK t CHI CKS CK CKE t CKA RAS CAS t t ...
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IS42S16100E, IC42S16100E Write Cycle / Page Mode CLK t CHI CKS CK CL CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Page Mode; Data Masking CLK t CHI t t CKS CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Byte Operation CLK t CHI CKS CK CL CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Byte Operation CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle, Write Cycle / Burst Read, Single Write CLK t CHI CKS CL CK CKE t CKA RAS ...
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IS42S16100E, IC42S16100E Read Cycle CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Auto-Precharge CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Full Page CLK t CHI CKS CL CK CKE t CKA RAS CAS t t ...
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IS42S16100E, IC42S16100E Read Cycle / Ping Pong Operation (Bank Switching CLK t CHI CKS CK CL CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle CLK t CHI t t CKS CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Auto-Precharge CLK t CHI t t CKS CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Full Page CLK t CHI CKS CK CL CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Ping-Pong Operation (Bank Switching CLK t CHI CKS CK CL CKE t CKA RAS CAS t ...
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IS42S16100E, IC42S16100E Read Cycle / Page Mode CLK t CHI CKS CK CL CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Page Mode; Data Masking CLK t CHI CKS CK CL CKE t CKA RAS CAS t ...
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IS42S16100E, IC42S16100E Write Cycle / Page Mode CLK t CHI t t CKS CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Page Mode; Data Masking CLK t CHI t t CKS CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Clock Suspend CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Clock Suspend CLK t CHI CKS CK CL CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS t t ...
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IS42S16100E, IC42S16100E Write Cycle / Precharge Termination CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle / Byte Operation CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Write Cycle / Byte Operation CLK t CHI CKS CL CK CKE t CKA RAS CAS ...
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IS42S16100E, IC42S16100E Read Cycle, Write Cycle / Burst Read, Single Write CLK t CHI CKS CL CK CKE t CKA RAS ...
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IS42S16100E, IC42S16100E ORDERING INFORMATION Commercial Range: 0°C to 70°C Frequency Speed (ns) 200 MHz 166 MHz 143MHz Industrial Range: -40°C to +85°C Frequency Speed (ns) 166 MHz 143MHz Please contact the Product Manager for leaded parts support. Integrated Silicon Solution, ...
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PACKAGING INFORMATION Plastic TSOP Package Code: T (Type II Millimeters Inches Symbol Min Max Min Ref. Std. No. Leads ( — 1.20 — A1 0.05 0.15 0.002 0.006 b 0.30 0.52 0.012 ...
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PACKAGING INFORMATION Mini Ball Grid Array Package Code: B (60-Ball SEATING PLANE mBGA - 10.1mm x 6.4mm ...